Transmitting data via SPI dma s32k324

[ann14]

I have been using SPI DMA for data transfer with the digital pins IC in S32K324. While the data transmitted is generally correct, we are encountering instances where incorrect data is transmitted.

Our analysis indicates that the MOSI line does not start sending data immediately upon clock enablement. This results in an additional bit (1) being added to the data, which affects the integrity of the data being transmitted.

I have attached screenshots that illustrate this issue for your reference.

Correct transmission of dataClock and MOSI line is synchronized correctlyIncorrect transmission of dataSlight delay in the MOSI line on clock enablement

[Senlent]

Hi@ann14

You can have a try to increase PCSSCK .

PCSSCK parameters correspond to SpiTimeCs2Clk

（Please ignore the configuration in the picture, I just want to tell you where to set this parameter）

[ann14]

Hi @Senlent,
according to the datasheet of the IC being used the chip select to clk time is 100ns. I gave this value and did the analysis but still it showed the same results.

[Senlent]

Hi@ann14

“according to the datasheet of the IC being used the chip select to clk time is 100ns”

I think 100ns should be the minimum allowed value, not the maximum value.

Because I can't tell the actual PCSCLK value from your picture, you can measure the actual PCSCLK value.
Then change the value of SpiTimeCs2Clk and send me a screenshot of the test result.

[ann14]

Hi @Senlent
You are correct the minimum value for the cs to clk is 100ns. But while testing we had varied the value of cs to clk from 100ns to the maximum value that is possible. Yet still the results where the same. If you would like i could provide you with the further result illustrations

[Senlent]

Hi@ann14

Yes,please, also could you please tell me which version of RTD you are using and show me the I2C parameter configuration in your S32 DS.

[ann14]

Hi @Senlent ,

I am currently using RTD 3.0.0 and SPI DMA configuration. I have attached the logs taken along 

[Senlent]

Hi@ann14

According to the MC33972 data sheet, I think you have set it wrong here.

I have change it to TRAILING.

[ann14]

Hi @Senlent
From this timing diagram how were you able to identify that data is sampled on the trailing edge.

[Senlent]

Hi@ann14

From this timing diagram, this should be sampled from the falling edge of SCK, not the rising edge.

[ann14 · Accepted solution]

Hi @Senlent
It is working now after changing it from leading to trailing. Thank You for the help.

[Senlent]

Hi@ann14

Thanks for your detail info, aslo,please share the slave device you're using, i want to see if there is anything that can be improved.

[ann14]

Hi @Senlent
MC33972ATEWR2 this is the slave device we are using