The frequency division problem of the PWM capture clock

[xingyun]

When the global frequency division of emios cannot be changed (changing it would affect the PWM output, and the PWM output and capture are the same emios0), now I want to achieve a 64-frequency division of the PWM capture clock. How can this be done? Are the several frequency divisions in the following EB configuration corresponding to the register frequency divisions as I have written? I can only set the frequency to 16 (Master Bus Prescaler). How to achieve 64-bit frequency division?

Clock Divider Value (1 -> 256)----GPRE

Master Bus Prescaler----UCPRE

Master Bus Alternate Prescaler----UCEXTPRE

Among them, I also don't quite understand UCPRE and UCEXTPRE.

Please help me. Thank you very much.

[xingyun]

I found that if I changed the division value of the Clock Divider (from 1 to 256), it was the GPRE register that would be affected. The Master Bus Prescaler has been modified to include the registers UCPRE and UCEXTPRE. Then I modified the Master Bus Alternate Prescale setting. However, none of the three registers related to the division were changed.
Could you please explain the relationship between these frequency division settings (Clock Divider Value (1 -> 256), Master Bus Prescaler, Master Bus Alternate Prescaler) in the EB and the registers (GPRE, UCPRE, UCEXTPRE)? My mind is a bit chaotic.

[Senlent]

Hi@xingyun

Please take a look at this picture.