Hi Yi_Feng,
Since it was working correctly for while, the configuration is correct.
And you don't use the RX FIFO (disabled in your project), therefore RXWATER is not used and the buffer depth is 1.
You could lose some data because of another interrupt which would lead to an overrun.
Can you enable error interrupts as well, especially START[OR], CTRL[ORIE].
Could you try using the highest priority level for the LPUART1 interrupt.
I have noticed that the interrupt priorities in you project are set incorrectly.
S32_NVIC->IP[LPUART1_RxTx_IRQn] = 0x7; // Not correct
S32_NVIC->IP[LPUART1_RxTx_IRQn] = 0x70; // Corect
It should be written to the 4 MSB of the IP bit fields.
Reading the DATA register clear the RDRF flag.
And the DATA register can be read by the debugger in Memory view or in the Register view as well not only by the core. Please close it during debugging.
Regards,
Daniel