Temporary Voltage Drop Observed During ADC Conversion on NXP MCU

[hants]

Hello,

I am experiencing an issue with ADC measurements on an NXP MCU and would like to ask whether this behavior is expected or if there are recommended configuration options to mitigate it.

Issue Description

When performing an ADC read, I observe a temporary voltage drop on the ADC input at the moment the conversion starts. As a result, the measured ADC value is lower than the actual steady-state input voltage that I expect.

This voltage drop is brief, but it is sufficient to cause incorrect readings, especially when the ADC value is used to distinguish between closely spaced voltage levels.

Observations

• The input voltage is stable when measured externally (e.g., with a multimeter or oscilloscope probe before conversion).

• At the start of ADC conversion, the voltage at the ADC pin briefly drops, then recovers.

• The ADC result appears to reflect this dropped voltage rather than the steady input level.

• This behavior is consistently reproducible.

Environment

• MCU: [S32K314]

• ADC instance: [AdcHwUnit 1_1ch]

• Software: [RTD R21-11 version 4.0.0 P19 / SW32K3 IPCF D2312]

• ADC clock: [160Mhz]

• Input source: 

  

Questions

1. Is this temporary voltage drop during ADC conversion a known or expected behavior related to the ADC sampling capacitor or input impedance?

2. Are there recommended settings (such as sampling time, power-down delay, or other ADC configuration options) to avoid or reduce this effect?

3. Is additional external buffering (e.g., an op-amp) generally required in this case?

4. Are there any NXP application notes or references that discuss this phenomenon in detail?

Any guidance or best practices would be greatly appreciated.

Thank you in advance.

[Senlent]

Hi@hants

In short, the problem is that the resistance value of the voltage divider resistor in the voltage divider circuit is too large, causing sampling distortion.

I recommend that you change the resistance value of R1000 to below 5K and try again.

https://www.nxp.com/docs/en/application-note/AN12217.pdf

https://www.nxp.com/docs/en/application-note/AN4373.pdf

[hants]

hi@Senlent

Thanks for the reply. I understand that the main issue is the high source impedance of the divider (R1000 = 33k, R1001 = 100k), and that reducing R1000 below 5k is the recommended solution.

Just to clarify, I previously mentioned S32K314 by mistake — the actual MCU is S32K358.

For the current hardware revision, changing the resistor values is difficult. According to AN4373, increasing the ADC acquisition (sampling) time can also help with higher source impedances.

On S32K358, would increasing the acquisition time (and/or lowering ADCK via prescaler) be sufficient to achieve stable 12-bit results with this divider (~25 kΩ Thevenin source impedance)?
If so, is there a recommended minimum acquisition time (in ADCK cycles or µs), and which RTD/ADC parameter controls it?

Thanks.

[Senlent · Accepted solution]

Hi@hants

You can calculate the channel sampling time yourself, which is related to the module clock and ST parameters.