Systick and stop mode

[Catosh]

Hi, 

according to my understanding, in stop mode the SysTick should be disabled (since it's clocked from core clock):

Nevertheless, in my design (s32K11x) looks like It's nod disabled and it's able to exit from stop mode. 

Is it due to the attached debugger? 

Since the debugger interrupt is not mapped to NVIC I suppose it could be active, but if the core is stopped it shouldn't. 

The code is really simple and generated using the SDK3.0.0:

uint8_t buff_out[]="Test\r\n";

int main(void)

{

CLOCK_DRV_Init(&clockMan1_InitConfig0);
PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);
UART_Init(&uart_pal1_instance, &uart_pal1_Config0);
UART_SendDataBlocking(&uart_pal1_instance, buff_out, sizeof(buff_out), 0xFFFF);

//Init systick here for 350ms operation
S32_SysTick->RVR = 0xFFFFFF;
S32_SysTick->CVR = S32_SysTick_CVR_CURRENT(0);
S32_SysTick->CVR = 0;
S32_SysTick->CSR = S32_SysTick_CSR_TICKINT(1) | S32_SysTick_CSR_ENABLE(1);
S32_SCB->SCR = S32_SCB_SCR_SLEEPDEEP(1);
SMC->PMPROT = SMC_PMPROT_AVLP(1);//VLPR and VLPS are allowed
SMC->PMCTRL = SMC_PMCTRL_RUNM(0) | SMC_PMCTRL_STOPM(0) ;//Normal mode run
SMC->STOPCTRL = SMC_STOPCTRL_STOPO(2);
STANDBY();
while(1){
UART_SendDataBlocking(&uart_pal1_instance, buff_out, 3,0xFFFF);
STANDBY();
//asm("nop");
}

}

void SysTick_Handler(void)
{
__asm("nop");//Just for breakpoints
}

Any hint on this?

Thanks and K.R.

Luca

[Manliangpai]

When I init the delay with the CSR enable(the source below), my PORTD_IRQHandler cann't work any more...Even if I adjust its NVIC IP priority【S32_NVIC->IP[PORTD_IRQn] = 0x00; 】。

Have you ever encountered similar problems？

If I delete this delay_init or set the CSR sidable, PORTD_IRQHandler work again.

void delay_init(void)
{
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE(0);
fac_us = 80000000 / 1000000;
S32_SysTick->RVR = 0xFFFFFFul; //重装载寄存器
S32_SysTick->CVR = 0ul; //当前计数
S32_SysTick->CSR = 0u; //控制寄存器
//S32_SysTick_CSR_TICKINT此位设为1一定要建立中断服务函数
S32_SysTick->CSR |= S32_SysTick_CSR_TICKINT(1u)|S32_SysTick_CSR_ENABLE(1)|S32_SysTick_CSR_CLKSOURCE(1u);
}

[dianabatrlova · Accepted solution]

Hi Luca,

Yes, it is due to the attached debugger.

Please, refer to section "39.4.5 Debug in low power modes" in the RM rev 9.

... the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state:

• all system clocks, except the core clock, are disabled,

...

I hope it helps.

Best Regards,

Diana

[Catosh]

Hi Diana, 

yes, you were able to solve my problem. 

One related question: I monitor the bus clock on the clockout pin, and I thought that it was disabled in stop1 - but I can see that it is present when I am stopped. 

Is it gated at a later stage than the sample point for clockout?

K.R.

Luca.

[dianabatrlova]

Hi Catosh,

I'm very sorry for the delay.

I have tested this issue and I can reproduce it, unfortunately, I have no details about this behavior yet.
I will let you know if I get more information.

Thank you for your understanding.

Best Regards,

Diana