Software Emulated EEPROM

[arkadyosh]

Hello,
I want to use data flash to software emulated eeprom. Hardware emulated eeprom existing in S32K is not sufficient for me, 4KB is not enough. In reference manual I find some limitations for program phrase command:
"A Flash memory location must be in the erased state before
being programmed. Cumulative programming of bits (back-toback
program operations without an intervening erase) within a
Flash memory location is not allowed. Re-programming of
existing 0s to 0 is not allowed as this overstresses the device."

I want to write smaller blocks of data than 8 bytes, so sometimes I need to overwrite existing data with the same data and this cause re-programming existing 0s to 0. It is strong not recommended to this? What conequences it have? Is this affect to flash endurance? How can I workaround this?
And one more question about flash endurance, in DataSheet rev 1 minimum was 1K and typical 50k cycles, in newest there's only minimum 1K. How much real cycles can I expect?

Thanks

[arkadyosh]

I have another question, what about interrupts when I writing or erase program flash or data flash? Did I need to disable it or it can be enabled? My interrupt vector is in RAM.

Regards,
Arkadiusz

[danielmartynek]

Hi Arkadiusz,

Please have a look at Table 33-6 Allowed simultaneous memory operations.

But If you have your interrupt handlers in RAM as well, it shouldn't be a problem.

Regards,

Daniel

[arkadyosh]

Hi Daniel,
Unfortunately, when I erase or write PFLASH and any intteupts is coming uC reset. When I test it, interrupt vector was in RAM but handlers in flash. Next step was put handlers to RAM section but no difference, uC still reset. So when erase or write to PFLASH, interrupts must be disabled, or enabled and under this operations any interrupt cant coming, or meybe I miss something? Please clarify.

Regards,

Arkadiusz

[danielmartynek]

Hi,

When you mask all interrupts, the PFLASH operations work correctly, right?

Does any of the interrupt handlers read the PFLASH block?

Regards,

Daniel

[arkadyosh]

Thanks Daniel for your answer.
Yes, when mask all interrupts write to PFLASH work correctly.
I find solution, in one of interrupts routine I call function placed in PFLASH, when placed it in RAM write to PFLASH with enabled interrupts work well.

Regards,

Arkadiusz

[arkadyosh]

Thanks for you answer. To be sure that after some time firmware/flash not crash I will avoid reprogramm zeros to zero.

Regards

[danielmartynek · Accepted solution]

Hello,

The note from the RM you mentioned says that the memory location must be in the erased state, which is logic 1, before new data are written.

During the programming of the Flash, ECC checksum is generated.

The programming operation of the Flash and the checksum is unidirectional, it can only move bits from the '1' state (erased) to the '0' state (programmed).

So once the ECC checksum has been generated, its bits cannot be changed from 0 to 1 again without an erase operation. Therefore, after a subsequent write to the same phrase, the ECC checksum will not match the stored data and this causes ECC errors.

The smallest amount of memory that can be erased is a sector which is 2K (D-Flash).

The minimal guaranteed cyclic endurance is 1K. The typical endurance is not stated because it depends on many factors.

Regards,

Daniel