Should I follow the evaluation board or AN5426 Design Guides for bypass decoupling capacitor spec?

[Poley]

Hi all,

I am laying up a new schematic at the moment and am placing the bypass capacitors. I was looking at the design guidelines document AN5426 and it suggest the following for the 100 pin version of the S32K144:

Whereas the development board which has the same microcontroller has this for the decoupling caps:

The S32K148EVB goes even further:

What is the best practice for this out of the 3?

Thank you!

[davidtosenovjan]

Third option would be the best from noise absorbing point of view but it is mainly needed to pay attention to decoupling capacitors' placement:

[Poley]

How comes the 3rd option has so many more when it is in the same device family? I am planning on putting my cap's on the underside of my board for my BGA uC to keep it as short as possible.

Is there such thing as too many decoupling caps? Or should I just follow the 3rd image and keep the smallest values as close as possible?

[davidtosenovjan]

In the third scheme there are only additional 1000pF capacitors, it is nothing against recommendation.
Usually it is needed to follow what is recommended, possible improvements are up to user.