SPI can't receive data normally

[chris_010]

hi ,

In my project, I use spi as slave to receive data(Interrupt mode).when I use SPI_0, every thing goes well,I can receive data normally.However when I use SPI_1 and SPI_3,I can't receive normally, but the callback shows spi data transfer end. I have checked the SPI configuration across these cases, no issues were found. Can someone help me,thank you. MY code is attached.

spi_1 configuration 

Lpspi_Ip_AsyncTransmit(&SLAVE_EXTERNAL_DEVICE_1, Spi_0_TxSlaveBuffer, Spi_0_RxSlaveBuffer, 9, lpspi_callback_int);

when master transmit data,  miso_received_flag  is successfully set to 1(the flag is set to 0 before master send data).

[VaneB]

Hi @chris_010 

The configuration looks correct. A few things to double‑check:

• Are you using an EVB or a custom board?
• Is the interrupt configured and enabled properly for that SPI instance?
• Have you tried using different pins?

BR, VaneB

[chris_010]

hi,VaneB

1、I use a custom board.

2、The interrupt is configured. Besides,  the callback function will not be executed if the interrupt is not registered, will it?

3、I have tried the other pins，It didn't work well either.

I think there might be something wrong. I attach my code, could you help me to check,thanks  a lot.

[VaneB]

Hi @chris_010 

Since you are working with a custom board, I want to make sure that there are no hardware‑related issues affecting the behavior you are observing.

If possible, please create a new project from scratch and use the attached .mex file and main.c file to test the behavior on your side. The provided code configures LPSPI1 and LPSPI3 as masters and performs a synchronous transmission using a hardware loopback configuration (SOUT connected to SIN on the same LPSPI instance). The example then compares the received data with the transmitted data to verify correct operation.

Note: I tested this same code on an S32K312MINI‑EVB. Due to the EVB’s hardware design, I had to reassign some of the pins, so small differences in pin configuration may exist compared to your custom board.

[chris_010]

hi,

I have done the test as you said. LPSPI_1 and LPSPI_3 worked well, the rx_buffer changed as expected. However in my project,LPSPI_1 and LPSPI_3 didn't work well, only LPSPI_0 worked, even though I tried to use them as the same way.

What may be the cause,Could you please help me figure out what the possible causes are? My code is not lengthy, and I have added detailed comments throughout the project. In my project, LPSPI is configured as a slave to receive data sent by peripheral devices and verify the received data.I would greatly appreciate your assistance with this matter.

[VaneB]

Hi @chris_010 

Thank you for performing the tests. This confirms that the issue is not hardware-related.

Since the same code works correctly on LPSPI0 but not on the other instance, let's verify whether Lpspi_Ip_IrqHandler is being called by the corresponding LPSPI ISR.

This is important because Lpspi_Ip_IrqHandler is responsible for processing the interrupt flags TDF, RDF, REF, and TEF.

When working in interrupt mode, this is one of the best checks you can perform.
If the handler is not being called:

• RDF (RX) interrupts won't be serviced
• TDF (TX) interrupts won't trigger data loading
• Error flags may occur without being handled

[chris_010]

hi, VaneB

Thanks to your suggestions,  I have identified several discrepancies in the SPI Interrupt Status Register, which are illustrated in the following three figures.

First, let me explain the usage of SPI_0 and SPI_1 in the project: both work as slaves receiving data from the same master. Please note that only two lines are used: SCLK and MOSI. Because the slaves only need to receive data. If needed, I can connect the MISO line,but due to hardware limitations, there’s no CS line.

init all pins, SPI SR status like this

then, invoking the two functions, the status registers is as shown in below the figure.

Lpspi_Ip_AsyncTransmit(&SLAVE_EXTERNAL_DEVICE_1, IO1_MCU_Tx_Buffer, IO1_MCU_Rx_Buffer, 54, IO1_spi_callback);
Lpspi_Ip_AsyncTransmit(&SLAVE_EXTERNAL_DEVICE_2, IO2_MCU_Tx_Buffer, IO2_MCU_Rx_Buffer, 54, IO2_spi_callback);

then, SPI master send data, after a little moment,  SPI_0 and SPI_1  SR status as show below,

It seems that, TDF of SPI_1 does't update, I don't know the reason.Do you have any suggestions for resolving this issue?

  

[VaneB]

Hi @chris_010 

The LPSPI module does support interfacing with external masters that provide only clock and data pins, meaning that PCS is not strictly required at the hardware level. For more details, please refer to Section 70.3.2.4 of the S32K3xx Reference Manual, Rev. 12.

However, it is important to note that the Lpspi_Ip driver and the SPI driver are not implemented to support this feature directly. These drivers are designed with the expectation that PCS handling is performed either by the peripheral hardware engine or through a GPIO‑based chip‑select. Therefore, if your design requires the PCS input to remain continuously asserted, the application must implement this behavior manually.

Additionally, since you intend to have both SPI instances active simultaneously and configured with the same IRQ priority, there is a possibility that one slave’s interrupt may be delayed. In such cases, underflow or overflow errors may occur due to late ISR servicing.

[chris_010]

hi, VaneB,

Thank you so much for your detailed explanation.

1.   I have read Reference Manual you mentioned.but I have a confusion: the configuration file is generated by the S32DS tool, and the generated structure is of const type. So how can I modify the registers mentioned in the reference manual? In addition, according to my understanding, the structure is used to initialize the SPI. If the relevant registers are not modified through the aforementioned structure, should I modify the relevant registers after the init process? Are there any relevant examples or interfaces?

Lpspi_Ip_Init(&Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_1_Instance_3);

 

 2. "Additionally, since you intend to have both SPI instances active simultaneously and configured with the same IRQ priority, there is a possibility that one slave’s interrupt may be delayed. In such cases, underflow or overflow errors may occur due to late ISR servicing."

====In my project, we won’t actually use two SPI ports to receive data simultaneously like this. Previously, when using SPI_0 for data reception, everything appeared to work normally, but after switching to SPI_1, data reception failed to function properly, even though the configuration and usage methods of the two SPI ports are identical. That’s why I’m testing both SPI ports to receive data at the same time for comparison and observation. Since our company has already produced a large number of PCB boards, I have no choice but to use SPI_1 instead of the original SPI_0—this is why I’m really in a rush to resolve this issue. Additionally, it seems there is a significant time difference between our regions. Does your company have Chinese colleagues who are familiar with SPI communication? Could you please help introduce one to me? Thank you very much.

 

[VaneB]

Hi @chris_010 

CFGR1[PCSPOLn] can be configured through the Peripherals tool in Lpspi driver by modifying the SpiCsIdentifier parameter.

However, CFGR1[AUTOPCS] cannot be configured in ConfigTools. To enable it, you must manually update the generated SPI initialization structure. Add LPSPI_CFGR1_AUTOPCS(1) to the CFGR1 assignment in the SPI controller SpiPhyUnit configuration, for example:

(uint32)(LPSPI_CFGR1_PINCFG(0U) | LPSPI_CFGR1_PCSPOL(1U) | LPSPI_CFGR1_MASTER(1U) | LPSPI_CFGR1_AUTOPCS(1) | LPSPI_CFGR1_SAMPLE(0U)),

Please note that since you are modifying generated files, any update made in ConfigTools will overwrite your changes. You will need to re‑apply this modification after regenerating the code.

If you require more extensive support, please contact your NXP representative or your local distributor (Distributor Network | NXP Semiconductors). You may also submit a support ticket. Be sure to use your company email address when contacting NXP so we can prioritize your request accordingly.

Thank you for your understanding

[chris_010]

Hi,

thank you so much for your support and advice.