S32k146 dma transfer

[S32k1]

Hi Team,

I need to know how to setup Tcds for my dma transfer, in my requirement I need to create an array of CHNC values ie, the array shall contain each measurement phase CH0C1 and CH1C1.

The PDB control register is used to configure the PDB for each measurement phase. In the Dma transfer descriptor the source is the first element of CHNC array, destination is the PDB's CHxNC1 register(32 bit transfer), source offset is 4 byte, transfer length is 8 bytes ( the CH0C1 and CH1C1 register value). At the end of transfer restore the original source/destination addresses(dma transfer can start from the beginning).

Simply I need to create an array of 2 values and these values should be copied in the corresponding Ch0C1 and Ch1C1 registers....Can you help how to implement this. Source addr is the 1st element of the array and the destination addr is the Ch0C1 register.

[PetrS]

Hi,

below setting would work, but do not tested it...

uint32_t src_array[2] __attribute__ ((aligned (32)));

void DMA_TDC_init(void)
{

PCC->PCCn[PCC_DMA0_INDEX] |= PCC_PCCn_CGC_MASK; // CGC=1: Clock enabled for DMA0

DMA->TCD[0].CSR &= 0xFFFFFFFF ^ DMA_TCD_CSR_DONE_MASK; // Clear Channel Done flag
DMA->TCD[0].SADDR = DMA_TCD_SADDR_SADDR(&(src_array)); // Source Address
DMA->TCD[0].SOFF = DMA_TCD_SOFF_SOFF(4); // Source Offset
DMA->TCD[0].ATTR = DMA_TCD_ATTR_SMOD(0) | // Source address modulo feature is disabled
DMA_TCD_ATTR_SSIZE(2) | // Source data transfer size: 1: 16-bit, 2=32-bit
DMA_TCD_ATTR_DMOD(0) | // Destination address modulo feature: 0=disabled, x= x power of 2 buffer[DMOD=4->buffer of 16bytes]
DMA_TCD_ATTR_DSIZE(2); // Destination data transfer size: 1: 16-bit, 2=32-bit
DMA->TCD[0].NBYTES.MLOFFNO = DMA_TCD_NBYTES_MLNO_NBYTES(8); // Minor Byte Transfer Count is 8-bytes
DMA->TCD[0].SLAST = DMA_TCD_SLAST_SLAST(-8); // Last Source Address Adjustment is -8
DMA->TCD[0].DADDR = DMA_TCD_DADDR_DADDR(&(PDB0->CH[0].C1)); // Destination Address of Buffer
DMA->TCD[0].DOFF = DMA_TCD_DOFF_DOFF(40); // Destination Address Signed Offset is 40, offset between CH0C1 and CH1C1
DMA->TCD[0].CITER.ELINKNO = DMA_TCD_CITER_ELINKNO_CITER(1) | // Current Major Iteration Count is 1
DMA_TCD_CITER_ELINKNO_ELINK(0); // The channel-to-channel linking is disabled
DMA->TCD[0].DLASTSGA = DMA_TCD_DLASTSGA_DLASTSGA(-80); // Destination last address adjustment is -80
DMA->TCD[0].BITER.ELINKNO = DMA_TCD_BITER_ELINKNO_BITER(1) | // Starting major iteration count is 1
DMA_TCD_BITER_ELINKNO_ELINK(0); // The minor channel-to-channel linking is disabled
DMA->TCD[0].CSR = DMA_TCD_CSR_BWC(0) | // BWC=0: No eDMA engine stalls - full bandwidth
DMA_TCD_CSR_MAJORELINK(0) | // The channel-to-channel linking is disabled
DMA_TCD_CSR_MAJORLINKCH(0) | // channel 1 will be called from ch0
DMA_TCD_CSR_ESG(0) | // The current channel TCD is normal format - No scatter/gather
DMA_TCD_CSR_DREQ(0) | // The channel's ERQ bit is not affected
DMA_TCD_CSR_INTHALF(0) | // The half-point interrupt is disabled
DMA_TCD_CSR_INTMAJOR(0) | // The end-of-major loop interrupt is disabled
DMA_TCD_CSR_START(0); // The channel is not explicitly started

}

BR, Petr

[S32k1]

Hi @PetrS 

In my project the required trigger chain is FTM0_INT -> PDB1_IN0 ->ADC1 -> ADC1_COCO->DMA TCD Linking.

Please clarify the below questions 

1.I need to know how to copy the external register values to the PDB register CH0C1 and CH1C1 which should be a 32-bit transfer.

2.Where to add the source address (global variable) and destination address (PDB CH0C1 and CH1C1 register.

3. What is meant by the config Source Last Address Adjustment and Destination Last Address Adjustment( in eb tresos I don't find any provision for adding the source and destination address)

4.Since the minor loop should run twice( to copy 2 external register value ), how to configure the minor loop count?

[PetrS]

Hi,

I do not work with eb tresos, so cannot suggest here. But RTD drivers contain several demo examples fro DMA transfers and ADC usage, so you can refer to it, if needed.

For question generally;
1) I posted possible DMA TCD configuration for desired DMA moves in previous reply
2) TCD's SADDR and DADDR registers holds source and destination addresses
3) Last address adjustment specify how many bytes have to be added/substracted after major loop is done. This is to return source/destination addresses to initial values
4) Minor loop count is determined by TCD's CITER/BITER registers, but here you do not need that, I think, you can have 1 minor/major loop.

BR, Petr

[S32k1]

Hi @PetrS ,

Thanks for the reply, also I have changed the configurations according to your previous message but the copying of array data(global variable) to the corresponding PDB1 register CH0C1 and CH1C1 is not happening. Can you please help me how to get it done.

[S32k1]

Hi @PetrS 

The issue is not solved yet. Can you please tell how to configure Dma transfer.

[PetrS]

Hi,

try to share project you have, but if done in eb tresos I will not check it.
Or share relevant register setting. 
When debugging, do you see DMA TCD is changing, so it is triggered at least?

BR, Petr