S32k146 SPI lines

[Benin_R]

I'm working with the S32K146 microcontroller and interfacing it with the ADS8341 ADC over SPI. In this setup, the S32K146 acts as the SPI master, and the ADS8341 is the slave device.

According to the timing diagram in the ADS8341 datasheet, the MOSI line is expected to stay low during the entire slave response phase (after the command is sent from the master). However, in our implementation, we observe that the MOSI line goes high at the end of the transaction, even though no pull-up or pull-down resistors are connected to the line.

We modified the LPSPI driver to tri-stating the MOSI pin. Still we are getting a high pulse after the slave talks. This doesn't align with the ADS8341's timing requirements.

My questions are:

1. Is this the expected behaviour of the LPSPI driver?
2. Is there a configuration in the LPSPI driver (or SDK) that allows us to keep the MOSI line low (driven low) during the entire transaction, including the slave response phase?
3. Has anyone encountered a similar issue when interfacing with ADCs like the ADS8341 that expect specific idle states on MOSI?
4. Would adding an external pull-down resistor be a recommended workaround, or is there a cleaner solution via software configuration?

Any insights or suggestions would be greatly appreciated!

Thanks in advance.

[danielmartynek]

Hi @Benin_R,

The LPSPI HW module allows these two options only:

In your use case, set OUTCFG to 1 = Output data is tris-tated when chip select is negated.

If the module tri-states the MOSI pin, the line is floating, and due to capacitance or leakage, it may appear to be driven/pulled during the transaction. To ensure MOSI is low when the module stri-states the pin, use an external pull-down.

The internal pull devices are weak and available for digital inputs only:

Regards,

Daniel