Greetings,
The S32K341 series MCUs feature a dual-core design, enabling the use of lockstep. However, ensuring the operational safety of the chip becomes questionable in the absence of safety measures for the peripherals. In the reference manual, the eDMA instances are mentioned with the line: "This chip has one instance of eDMA without any lockstep." This raises a concern as the peripherals, buses, etc., are shared between the cores. My concern is that the effects on these peripherals due to electrical harsh environments may render the dual-core lockstep redundant.
I would like to inquire whether my concerns make sense. If they do, how can one ensure the operational safety of the chip when both cores are sharing the same peripherals?
Thanks in advance.
KadirY
Solved! Go to Solution.
Hello,
Sure, I will explain it below.
The memories are physically designed to spread across the memory field.So even if there is ionizing particle it wont affect the whole address when read. Even if it change the charge in one cell, this will be corrected via ECC. Covered by EDC.
Second E2E will ensure the correct communication via buses.
Next there are multiple safety mechanisms, like FCCU, RCCU, STCU which will cover tests, reporting and redundancy.
Please dive deep in the safety manual an reference manual safety mechanisms to understand the protection applied.
Best regards,
Peter
Hello,
As the reference manual express:
My concern is that the effects on these peripherals due to electrical harsh environments may render the dual-core lockstep redundant.
There are implemented various ECC. E2E, Register protection, etc... mechanism which ensures the safe signal transfer trough busses.
Best regards,
Peter
Thank you for the detailed response. However, I remain uncertain about whether the built-in mechanisms effectively safeguard against single-event upsets in general. Could you please clarify whether the S32K3XXX series is resilient against single-event upsets, both for cores and peripherals?
Thanks in advance,
KadirY
Hello,
Sure, I will explain it below.
The memories are physically designed to spread across the memory field.So even if there is ionizing particle it wont affect the whole address when read. Even if it change the charge in one cell, this will be corrected via ECC. Covered by EDC.
Second E2E will ensure the correct communication via buses.
Next there are multiple safety mechanisms, like FCCU, RCCU, STCU which will cover tests, reporting and redundancy.
Please dive deep in the safety manual an reference manual safety mechanisms to understand the protection applied.
Best regards,
Peter