S32K366 GMAC Configuration Inquiry with LAN8720 PHY

[zhangzhixing]

Recently, I designed a circuit using S32K366, where the MCU controls another Ethernet module on the board via a PHY chip (LAN8720). The LAN8720 has successfully established a link with the onboard Ethernet module, auto-negotiated to 100Mbps full-duplex.

I conducted three tests:

1. ‌Internal MAC Loopback Test‌:

   • Followed the Gmac_Ip_InternalLoopback_S32K396 example to configure the S32K366 MAC in loopback mode. After programming, the MAC successfully received its own transmitted data using:
     cCopy Code
     do { Status = Gmac_Ip_ReadFrame(INST_GMAC_0, 0U, &RxBuffer, &RxInfo); } while (Status == GMAC_STATUS_RX_QUEUE_EMPTY);
   • Observed Des3 = 0x03000040 in descriptors.

2. ‌PHY (LAN8720) Local Loopback Test‌:

   • Configured MAC in non-loopback mode and enabled LAN8720’s local loopback (PHY echoes MAC’s TX data back to RX).
   • Confirmed waveforms on MAC’s RXD0/RXD1/RXDV pins via oscilloscope.
   • However, the same Gmac_Ip_ReadFrame() loop hung indefinitely (Status remained GMAC_STATUS_RX_QUEUE_EMPTY).
   • Descriptor Des3 showed 0xC1000000.

3. ‌Normal Mode (End-to-End Communication)‌:

   • Configured LAN8720 in normal mode. MAC TX data reached PHY’s differential outputs, and the Ethernet module replied.
   • LAN8720 forwarded the module’s data to MAC via RMII (RXD0/RXD1), but Gmac_Ip_ReadFrame() again failed to capture data (same behavior as Test 2).
   • Des3 remained 0xC1000000.

‌Additional Checks‌:

• Verified RMII clock (50MHz) and data timing—no significant issues observed.

‌Question‌:
Beyond disabling MAC loopback (as in the official internal loopback test), what additional MAC configurations are required for S32K366 GMAC to communicate via LAN8720? Specifically:

• Are DMA or other peripheral settings mandatory?
• Why does Des3 differ between loopback/non-loopback modes, and how does this affect reception?

Looking forward to your guidance.

Best regards,
Zhang Zhixing

[PavelL]

Hello @zhangzhixing ,

Thank you for the detailed description.
May I ask which version of the RTD you are currently using?

Below are a few suggestions based on the RTD 4.0.0 and the lwIP example for S32K396. I hope they help clarify the configuration:

1. Pin Configuration
The pin settings in the Gmac_Ip_InternalLoopback_S32K396 example look correct.
You might consider starting with the Fastest drive strength for output pins.

2. Clock Configuration
The EMAC clock shall be configured for RMII as shown on the picture (from S32K344):

PavelL_0-1750839936554.png

Based on the lwIP example, please verify the DCM_GPR configuration:

/* Set RMII configuration for EMAC in DCM module */

IP_DCM_GPR->DCMRWF1 |= DCM_GPR_DCMRWF1_MAC_CONF_SEL_MASK;

This line is typically placed very early in the initialization sequence, often before any clock or peripheral setup.

Please note: This configuration differs from the one used on S32K344, as the DCMRWF1 register layout has changed in the S32K396.

3. PHY Reset Sequence
Ensure the PHY is properly reset and stabilized before EMAC initialization:

• A good place for the PHY reset is after Siul2_Port_Ip_Init() and before Clock_Ip_Init().
• Make sure to insert a delay (typically 3-5 msec - depends on used PHY) after releasing the PHY reset to allow it to complete internal initialization.

Also verify:

• The PHY has completed its internal startup sequence.
• The RMII clock (50 MHz) is present and stable before calling Clock_Ip_Init() and initializing the EMAC.

Please feel free to use the lwIP example as a reference. However, all the checks and updates mentioned above are still necessary to ensure proper functionality.

Best regards,

Pavel