Hello,
Due to continuous resetting its very difficult to debug.
Simply do hot attach with your debugger. This will stop code execution, so no SW reset will be triggered.
For example use Lauterbach debugger and do UP right after the power on reset.
Can i use core 0 without RTOS and Core 2 with Free RTOS?
Sure, there is no issue here. Make sure you share resources between cores correctly.
To use CAN in core 2, do I need to anything specific in project setting | Linker file | any other XRDC register? Just normal CAN configuration is enough.
It depends. If only core2 will access the peripheral, then you do not have to worry about conflicts.
Suggested steps:
- Decide which FlexCAN instance Core2 will own (e.g., FlexCAN0).
- In your Core0 init, set clocks and SIUL2 mux for the chosen CAN pins (or do it on Core2 if your boot model allows).
- Configure XRDC: assign Core2’s domain and permit access to the FlexCAN instance (PAC) and any RAM you’ll use for CAN buffers (MRC).
- In Core2 project, configure Can_43_FLEXCAN and IntCtrl_Ip so FlexCAN interrupts are enabled and handled on Core2.
- Build & load two images (Core0 & Core2). Verify CAN RX/TX and interrupts on Core2.
Best regards,
Peter