S32K358 multi core debug issue

[nirmal_masilamani]

Hello Team,

Currently i am working with s32k358 custom board, i am facing hard fault issue when i try to debug both cores.

Controller resetting continuously.

I have attached my code. one core with FREE RTOS, another core without RTOS.

[petervlna]

Hello,

Controller resetting continuously.

Check the reason for resets. Read RGM FES and DES registers to see the reset sources.

Best regards,

Peter

[nirmal_masilamani]

Hello @petervlna ,

Thanks for the reply.

Due to continuous resetting its very difficult to debug.

My doubt is, 

Can i use core 0 without RTOS and Core 2 with Free RTOS?

To use CAN in core 2, do I need to anything specific in project setting | Linker file | any other XRDC register? Just normal CAN configuration is enough.

[petervlna]

Hello,

Due to continuous resetting its very difficult to debug.

Simply do hot attach with your debugger. This will stop code execution, so no SW reset will be triggered.

For example use Lauterbach debugger and do UP right after the power on reset.

Can i use core 0 without RTOS and Core 2 with Free RTOS?

Sure, there is no issue here. Make sure you share resources between cores correctly.

To use CAN in core 2, do I need to anything specific in project setting | Linker file | any other XRDC register? Just normal CAN configuration is enough.

It depends. If only core2 will access the peripheral, then you do not have to worry about conflicts.

Suggested steps:

• Decide which FlexCAN instance Core2 will own (e.g., FlexCAN0).
• In your Core0 init, set clocks and SIUL2 mux for the chosen CAN pins (or do it on Core2 if your boot model allows).
• Configure XRDC: assign Core2’s domain and permit access to the FlexCAN instance (PAC) and any RAM you’ll use for CAN buffers (MRC).
• In Core2 project, configure Can_43_FLEXCAN and IntCtrl_Ip so FlexCAN interrupts are enabled and handled on Core2.
• Build & load two images (Core0 & Core2). Verify CAN RX/TX and interrupts on Core2.

Best regards,

Peter

[nirmal_masilamani]

Hello @petervlna ,

Thanks for your inputs,

• Configure XRDC: assign Core2’s domain and permit access to the FlexCAN instance (PAC) and any RAM you’ll use for CAN buffers (MRC).

Is there any example available or documents for XRDC configuration?

To use Free RTOS, in core 2, what's needs to done?

[nirmal_masilamani]

Hello Team,

I am trying use multi core in S32K358 in custom board.

I simply configured LED in Core 0 and UART in Core 2, But after some time, Controller restting ( Not fixed interval ).

Resetting reason from Power_Ip_GetResetReason -. Power on Reset.

I tried configuring XRDC for UART, but after RM init system goes to hard fault.

[petervlna]

Hello,

Power_Ip_GetResetReason -. Power on Reset.

Hmm, this looks like you lost power to your uC.

Was there a reset performed by your SBC chip? Did you monitor HVD, LVD and reset line by oscilloscope to see if the voltages was OK when reset occurs?

Best regards,

Peter

[nirmal_masilamani]

Hello @petervlna ,

Thanks for your reply.

I have monitored Reset Pin, for every reset-> reset pin drops to low.

Could you please share details for HVD and LVD pin details?

Another observation, resetting not happening if I program core 2 with empty while (1) loop.

Resetting happening only, if there some logic in core 2 (even with LED link).

[petervlna]

Hello,

Could you please share details for HVD and LVD pin details?

Check the schematic of your board to see where exactly is HV_A routed.

For your S32K3 device (e.g., S32K358 in your AEB project), the core voltage (V11) is generated internally using the high‑voltage input domain VDD_HV_A.

Another observation, resetting not happening if I program core 2 with empty while (1) loop.

Resetting happening only, if there some logic in core 2 (even with LED link).

That is a good point. Do you use NXP evalaution board?

If not, you power supply might not be strong enough to execute task on 2 cores and once second core draw higher current the LVDs will reset micro.

But I expect there will be some HW resource sharing issues which will lead to reset. For example not servicing the SWT for core2, etc...

Still best way is to look at FCCU NCFS registers for faults and RGM FES and DES for reset reasons.

Best regards,

Peter

[nirmal_masilamani]

Hello @petervlna ,

One more observation, resetting happening only if clock is enabled.

If clock is not explicitly initialized in both cores, resetting not happening.

Is there anything I need to do with clock configuration for multi core?

[petervlna]

Hello,

You can check and try following example:

https://community.nxp.com/t5/S32K-Knowledge-Base/S32K358-Multicore-Start-CM7-2-from-CM7-0/ta-p/19238...

Best regards,

Peter

[nirmal_masilamani]

Hello @petervlna ,

Thanks for the reply.

I used same example only, even in that example if i do clock_init() system resetting.

[petervlna]

Hello,

OK, thanks for clarification.

Changing the clock, will significantly increase the power consumption.

I expect you scenario is as follows.

You start second core, change the clocks and power source is not able to deliver required power in the time, therefore the LVDs ?(low voltage ddetectors) will trigger reset.

Micro starts and reset over and over after reset.

Measure you power source (SBC) along with reset line to see if the reset match the voltage drop on VDD_HV_A or on SBC.

Best regards,
Peter