S32K358 multi core data sharing

[nirmal_masilamani]

Hello ,

I am trying to use shared memory in s32k358 multi core.

I am following user define example, 

When i try to assign some value in buzzer_state_shared_data_U32 ( currently only core 0 is accessing this memory), core 0 is hanging and swt resetting the controller.

But when i flash the code in debug flash, its running properly. With power on reset, core 0 is hanging. 

Why its running properly in when flashing and not running in power off and on.

[Julián_AragónM]

Hello @nirmal_masilamani,

But when i flash the code in debug flash, its running properly. With power on reset, core 0 is hanging. 

This is most likely caused by ECC RAM error. Usually, debuggers initialize the ECC on volatile memories, however, when powering on and off, debugger does not initialize RAM, and hardfault occurs when trying to access memory.

This is usually done in the startup code, before main.

The section should be also configured as non-cacheable.

Regarding your second issue: but when i try to access it from timer ISR or OS task, core 0 going to hardfault.

You can try to trace back your hardfault. Halt the core in the HardFault_Handler(), and find the SP value in the core registers: How To Debug A Fault Exception On ARM Cortex-M(V7M) MCU(S32K3XX).

Best regards,
Julián

[nirmal_masilamani]

Hello @Julián_AragónM ,

Thank you for your quick response,

I check the startup files, SRAM Init is happening.

I have attached my startup files and linker files. Please support me to resolve this issue

[nirmal_masilamani]

Hello @Julián_AragónM ,

Please support on this query. What i am missing here?

[Julián_AragónM]

Hello @nirmal_masilamani,

Are you able to access shared memory in main() after POR reset without debugger? Was the issue RAM initialization?

but when i try to access it from timer ISR or OS task, core 0 going to hardfault.

Were you able to identify the fault type as I mentioned in my previous reply?

Have you also made sure the variable is placed in a non-cacheable area, or the cache is disabled?

As suggestions:

Keep volatile on core1Status and use __DMB()/__DSB() barriers on both the read (Core0) and write (Core1) sides.

Your issue could also be caused by MPU configuration, if MPU_ENABLE is defined, please call the MPU config before any ISR or OS task starts executing.

You can refer to the following links: Arm Cortex-M7 Devices Generic User Guide r1p2 & AN14715: S32K3XX Hardware Resource Isolation and Protection.

Best regards,
Julián

[nirmal_masilamani]

Hello,

When i access shared memory in main(), its working fine even in power off and on, but when i try to access it from timer ISR or OS task, core 0 going to hardfault.

Please support me in this.