S32K358 Multicore share memory

[nirmal_masilamani]

Hi,

I am currently working with s32k358 multicore, i am trying use shareble memory for IPC.

i am trying use core0status and core1status variable for IPC data sharing.

but both variable declared in same memory, so each core overwriting the value.

Address of core0status and core1status, interchanged in each core. 

What i am missing here? Please find the attached code.

[Julián_AragónM]

Hi @nirmal_masilamani,

Shared variables are initialized only once by CM7_0 (boot core), not by CM7_1 (secondary core). Core0 will do the data copying from ROM to RAM for shared global variable with init values, while Core1 will ignore data copying and just use them in code.

Linker files between Core0 & Core1 should look something like so:

I've sent you a private message with some materials for S32K3 Dual Core and Memory Sharing between cores.

Best regards,
Julián

[nirmal_masilamani]

Hello @Julián_AragónM ,

Thank you for your reply.

Shared memory issue, resolved by following the document, but i want to configure sema42 driver, how can do i that?

Could you please provide some document for that.? i am using s32ds v3.5 RTD 4.0.0

[Julián_AragónM]

Hi @nirmal_masilamani,

There is also a training presentation:  S32K3 RTD XRDC, SEMA42, MPU, XBIC and INTM Training Presentation. However, it is under secure files for the S32K3. If you do not have access, you may need to upload an active NDA and request it. Please refer to Secure Access Rights FAQs | NXP Semiconductors.

Publicly, there are these two application notes: 

• AN13024: S32G2 Extended Resource Domain Controller (XRDC) Application Note.
• AN14715: S32K3XX Hardware Resource Isolation and Protection

While the modules are very similar, there are some differences between S32G and S32K devices, so please read the application note carefully.

Best regards,
Julián

[nirmal_masilamani]

Hi @Julián_AragónM ,

Thank you for the reply.

I have NDA signed acc, but still unable to access the secure file.

Another, i have referred share memory program for S32K324 , but in my program 

#define CORE_DOMAIN_ID (IP_XRDC->HWCFG1) always show 0 in both core.

What am i missing here?

[Julián_AragónM]

Hi @nirmal_masilamani,

XRDC should be properly initialized to assign DID=0 for CM7_0 and DID=1 for CM7_1. Please check the XRDC Domain Assignment. You can refer to the RTD example: 

As for the secure file, you need to request access to it. Please refer to the FAQ I've previously shared.

Best regards,
Julián

[nirmal_masilamani]

Hello @Julián_AragónM ,

I followed same example, still both core return 0 as domain ID.

do i need to init sema in core 2 also?

[Julián_AragónM]

Hi @nirmal_masilamani,

No. Most likely XRDC is not set correctly. By default, both CM7_0 and CM7_1 have DID = 0. I've sent you a private message regarding XRDC configuration.

Best regards,
Julián