S32K358 Legacy RX Fifo with DMA vs enhanced RX Fifo DMA

[saikiranG]

Why doesn’t S32K3 RTD support DMA batching (major loop > 1) for Legacy Rx FIFO, while Enhanced Rx FIFO does?

I'm using S32K358 FlexCAN with Rx FIFO + DMA. In Enhanced Rx FIFO, the RTD configures DMA with minor loop = 80 bytes and allows batching via u32NumOfMbTransferByDMA (N frames), so DMA_COMPLETE fires after N frames. For Legacy Rx FIFO, so DMA_COMPLETE occurs per frame, with no batching option.

• Is the lack of DMA batching for Legacy Rx FIFO an intentional RTD design choice or a hardware limitation of the legacy FIFO path?
• Could RTD safely support a signed source offset and major loop > 1 for Legacy Rx FIFO to enable batching?
• Any recommended workaround to reduce IRQ rate with Legacy FIFO + DMA?

Configuration: S32K358, RTD 6.0.0, Legacy Rx FIFO + DMA vs Enhanced Rx FIFO + DMA.

[Senlent]

Hi@saikiranG

Legacy FIFO is a feature retained from K1 on K3.

This legacy FIFO has a message depth of 6, so it can only receive classic CAN 2.0 messages and cannot receive CAN FD messages.

This is also mutually exclusive with the enhanced FIFO feature; if legacy FIFO is enabled, enhanced FIFO cannot be enabled.

Demo for your reference:

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-FlexCAN-Ip-TX-RX-EnhanceRXFIFO-DMA-...

[saikiranG]

Got it. Is there any way I can get DMA complete interrupt after the depth of FIFO (like 5 for say) like we have in case of enhanced rxFifo? Currently, I still get DMA complete interrupt after every time DMA transfers from Fifo output when frame's available to SRAM. This case is supported in enhanced rx Fifo based on the u32NumOfMbTransferByDMA configuration.

[Senlent]

Hi@saikiranG

The legacy FIFO does not support watermark configuration (Enhanced FIFO does support watermark configuration).

For legacy FIFO,as long as there is a frame in the current FIFO, a DMA interrupt request will be generated.

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When at least one frame available to be read from the FIFO, IFLAG1[BUF5I] (Frames available in Legacy RX FIFO) is set. A DMA request is generated simultaneously. Upon receiving the request, the DMA controller can read the message (accessing the output of the Legacy FIFO as a message buffer).

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