S32K348 ECC set

[youngkin]

hello, 

I have three questions that need help to answer, thank you！

1. can you provide a ecc  sample 

2.  how  can  i  verify the function ?

[petervlna]

Hello,

ECC tests are part of the eMCEM driver of SAF / SPD package.

You will find there examples with sophisticated checks for verification.

https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-fra...

If you prefer your own code / hard coded tests, then refer to the reference manual:

• Pre‑reqs:

  • RTD clock init configured so ME enables clock to EIM and ERM. If EIM regs don’t respond, it’s almost always a clock gating issue—enable the partition/COFB clock first.
  • Startup code initializes ECC for SRAM (write‑through once) before reads, otherwise first read can trigger multi‑bit errors. (Zephyr & SEGGER notes highlight this as a common pitfall.)
  • Identify an ERM channel that corresponds to the memory master/region you’ll access (e.g., CM7_0 reading SRAM). Channel mapping is in RM; public tutorials summarize the concept.

  High‑level flow:

  1. Enable clocks for EIM & ERM
  2. Configure ERM: enable “single‑bit corrected” interrupt + “multi‑bit error” interrupt for the relevant channel
  3. Set up EIM: choose the SRAM channel, set one data/check bit for injection (single‑bit)
  4. Perform a read of any address in that memory region → ERM should report a correctable error
  5. Clear, then set two bits in EIM (double‑bit)
  6. Read again → expect non‑correctable → your handler should capture/contain the fault

  1. Optionally, scrub (rewrite) the affected location to clear corrected syndromes

Best regards,

Peter