S32K322 Dual Core debugging with J-link

[AbdNxp]

Hello NXP Support team,

Target: S32K322

Debugger H/W: J-link/J-trace.

Currently, my application launches and hits cm7_0 main, when run , the IDE get hanged.

I wanted your expert guidance to do dual core debugging, where core0 and core1 runs independently, resetting core1 does not reset core0 and vise-versa.

How I can put break-point in core1 application.

Currently I am using an application attached below.

What I am trying to do is core0 does so communication on UART while core1 toggles LED. The code is not complete, but you may still refer it.

Additionally, wanted to know what if I initialize UART0 from core0 and UART1 from core1 will it cause any issue.

If I use a different GPIO configuration for core0 and core1, will it conflict each other? 

Thanks 

[danielmartynek]

Hi @AbdNxp,

The SEGGER plugin in S32 Design Studio supports launching a debug group, which allows you to program and debug multiple cores simultaneously.

https://community.nxp.com/t5/S32K/How-to-Use-Jlink-to-Debug-S32K324-Dual-Core-On-S32KDS3-5/td-p/1924...

... resetting core1 does not reset core0 and vise-versa.

Despite the dual-core architecture, you cannot reset one core independently while the other continues running. This limitation is due to the shared reset architecture of the S32K3xx family. A reset event affects both cores, making isolated core resets infeasible during debugging.

Additionally, wanted to know what if I initialize UART0 from core0 and UART1 from core1 will it cause any issue.

If I use a different GPIO configuration for core0 and core1, will it conflict each other?

You can safely initialize UART0 from CM7_0 and UART1 from CM7_1. This setup is valid as long as each core accesses its designated peripheral without overlap.

To enforce access control between cores, you can configure XRDC (eXtended Resource Domain Controller):

• Create separate domains for CM7_0 and CM7_1.
• Assign peripherals like LPUART modules and GPIOs to specific domains.
• This ensures that CM7_0 cannot access CM7_1’s resources, and vice versa.

Regards,

Daniel

[AbdNxp]

I have already using the Group Debugging, the issue is S32DS Ide getting hanged or become non-responsive during the debug session.

See below image

And also If I put a break somewhere in While(1 ) loop of point in CM7_1, break point does not hit. 

[danielmartynek]

Hi @AbdNxp,

I cannot reproduce this behavior.

It seems that the second debug session for CM7_1 debugs code from the same memory region (0x400000) as the first debug session.

Can you maybe share the test project?

Thank you

[AbdNxp]

Hi Daniel,

Attached the project.

[danielmartynek]

Hi @AbdNxp,

I still cannot reproduce the issue.

However, please note that in the S32DS IDE, this functionality is provided by a SEGGER plugin.

I recommend reaching out to SEGGER support as well.

Thank you

[AbdNxp]

Hi Daniel,

So you are able to run the application with J-link/J-trace Pro ? 

I tried multiple time but I could not make it run.

[danielmartynek]

Hi @AbdNxp,

Yes, I can debug multicore application with J-trace from S32DS IDE.

Unfortunately, I don't have any S32K322 HW right now.

Here you can see that both cores work in different flash blocks, unlike in the screenshot you posted.

I have tried loading your application on S32K324 which should be possible, but I get a different error than you.

The debug configuration of the second core should have this disabled:

But you have that in the project.

Regards,

Daniel