S32K312 sCheck to open the ECC test, run the sCheck_CortexM7_ErrRead function to enter the hardfault

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S32K312 sCheck to open the ECC test, run the sCheck_CortexM7_ErrRead function to enter the hardfault

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Yongxingjia
Contributor II

S32K312 sCheck to open the ECC test, run the sCheck_CortexM7_ErrRead function to enter the hardfault.

According to the description in the S32K3_SAF_SCHECK_UM.pdf, the ramcode_no_cacheable segment has been placed in the Ram region, but the assignment of a local variable in the sCheck_CortexM7_ErrRead function will trigger a Hardfault. This address has been configured in the MPU to execute code, what is the possible reason here?

Yongxingjia_0-1719645443720.png

Yongxingjia_1-1719645773756.png

Yongxingjia_2-1719645831842.png

Before running uint64 result=0ULL;

Yongxingjia_3-1719645874487.png

After running uint64 result=0ULL

Yongxingjia_4-1719645979316.png

Is there any way to troubleshoot this problem?

S32K3 SAF 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Yongxingjia,

What is the address of the result variable?

What do you see in the MMAR register? (MMARVALID = 1)

It detects a fault exception on a write, not code execution.

I see several regions overlapping, is it intended?

Did you enable sub-regions in that regions.

Also, the base address of a region should be aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000. I don't see that in your MPU configuration.

https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-U...

 

Regards,

Daniel

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Yongxingjia
Contributor II

Hello,Daniel:

I configured it with reference to the demo of the S32K344,and the demo also overlapping it.Yongxingjia_0-1720073793703.png

Now I've also modified the configuration of the MPU, but I'm getting a new problem

Yongxingjia_1-1720073984305.png

When "204102c2: str r2, [r0, #0]"is executed in the sCheck_CortexM7_ErrRead function, the vector table is relocated to the 0x20410480, 0x20410480 the storage is the 0xBF00BF00

Yongxingjia_2-1720074148982.png

 

When 204102fe: ldrd r0, r1, [r1] is executed in the sCheck_CortexM7_ErrRead function, the code executes exceptionally

Yongxingjia_3-1720075854639.png

What are the precautions about ECC in the sCheck integration, ECC-related testing and debugging have been for a long time, and there has been no progress, and the user manual is not very clear, or can you provide a S32K312 Demo project for reference, thank you!

Yongxingjia_4-1720076527615.png

 

 

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RadoslavB
NXP Employee
NXP Employee

Hello @Yongxingjia ,

please could you:
- specify which sCheck test exactly causing this issue?
- find out the address for these symbols: "sys_stack_init", "sys_vec_0"
- which compiler are you using?

Kind Regards,
Radoslav

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