S32K312 Nvic subpriority issue

[arielcolombo]

Hello,

I am facing an issue with the interrupt priority configuration on the S32K312. I have set the registers to have 2 groups and 2 subpriorities. However, I am observing unexpected behavior:

An interrupt with group priority 0 and subpriority 1 sometimes executes before another interrupt with group priority 0 and subpriority 0. If I change the subpriority from 1 to 2 in the first interrupt, everything works correctly, but I do not understand why this happens.

Specifically, the problematic interrupt is a SAOC (ADC Channel 9) that competes with an MC (Counter Channel 23) which handles the counter bus. The MC is configured to generate an interrupt on "Internal Counter Match End" when the register reaches 65535, setting the flag in 0 ticks.

Additionally, I have observed that the SAOC detects the issue when the match occurs very close to the overflow, and it might be waiting while the SAIC (Channel 0), which has group priority 0 and subpriority 0, is being serviced. This SAIC seems to work correctly.

// Example simplification

__NVIC_SetPriorityGrouping(5u);

// SAOC priority 0, subpriotity 0 CH9
// SAIC priority 0, subpriotity 0 CH0
// MC priority 0, subpriotity 1  CH23 EMIOS MODE FOR MC 0b0010010
prio = NVIC_EncodePriority(5, priority, subpriority);

__NVIC_SetPriority(irq, prio);
__NVIC_EnableIRQ(irq);

Could someone help me understand why this behavior occurs and how to fix it?

Thank you in advance.

#S32K312

[davidtosenovjan]

 

 

Preemption defines behavior of “nesting”.

It means if two interrupt sources belongs to same group priority, they are not interrupting each other during interrupt processing of one of this interrupt source (they are not nested). If they have different group priority, they will be nested.

Check setting in the core register AIRCR[PRIGROUP], to check which bits defines priority and which sub-priority.

[arielcolombo]

Hi David,

Could you help me understand if setting the value 5 in the AIRCR[PRIGROUP] register effectively gives me 2 bits for group priority and 2 bits for sub-priority?

Regarding your previous response, I understand that there will be no preemption between interrupts of the same group priority, and this is not what I am looking for. What I need is for the system to handle the next interrupt based on its sub-priority once the highest priority interrupt has finished, since they all belong to the same group priority.

To simplify my scenario: while handling an interrupt with the highest possible priority, if 2 additional interrupts of the same group but different sub-priority are generated, the system does not respect handling the interrupt with sub-priority 0 and sometimes handles the one with sub-priority 1. The solution I found was to change the sub-priority from 1 to 2, which works correctly, but I do not understand if I am misconfiguring the AIRCR[PRIGROUP] register and the bits I believe to have configured are not doing what I expect.

Thank you.