S32K312：How to set low voltage detection for chips

[Zhaohguanyu]

Hello NXT Team

I can only find LVRBLPEN, with the following description

LVRBLP enable bit during LPM Controls whether the low-voltage reset detection (LVRBLP) on the VDD_HV_B power domain is active or inactive in LPM

However, there is no VDD_HV_B on pin 312, which has left me confused

best regards

Zhao

[petervlna]

Hello,

LVRBLPEN controls whether the Low Voltage Reset detection for the VDD_HV_B domain remains active during Low Power Modes (LPM).
The term VDD_HV_B refers to an internal power domain, not a physical pin. It’s part of the high-voltage domain inside the MCU that powers certain peripherals and logic blocks.

Here is the power domain for S32K312:

and supplies table for S32K312:

The manual is common for the S32K3xx family. So, often all features are described in general, and then it is necessary to pay attention to what is really valid for your device derivative.

Best regards,

Peter

[Zhaohguanyu]

Hello Peter

Thank you for your reply
May I ask if I want to disable the low voltage reset function,
Which register do I need to manipulate?
It seems that setting the LVRBLPEN register to 0 will prevent the MCU from resetting in LPM mode
Which register should be controlled in other modes?

Best regards

Zhao

[petervlna]

Hello,

May I ask if I want to disable the low voltage reset function, Which register do I need to manipulate?

You cannot disable LVD on this device. It will lead to unexpected behavior and definitely to reset at the end.

I also see no reason for such as we guarantee uC operation only withing spec.

Best regards,

Peter

[Zhaohguanyu]

Hello Peter

Thank you for your reply

Can I understand it this way, LVD can only be turned off in LPM mode?
If it cannot be turned off, can we configure this threshold?
I am currently testing that a reset will be triggered at around 2.8V

Best regards

Zhao

[petervlna]

Hello,

Can I understand it this way, LVD can only be turned off in LPM mode?If it cannot be turned off, can we configure this threshold?

I am currently testing that a reset will be triggered at around 2.8V

No you cant configure its threshold. It is fine tuned in NXP factory.

Please respect the operation conditions defined in the datasheet.

Best regards,

Peter

[Zhaohguanyu]

Hello Peter

Thank you for your reply

My current test result is

The chip will reset directly at around 2.8V,This is as expected

But 5.8V will not reset

This interrupt must be paired and the reset function must be called within the interrupt itself

May I ask if the different manifestations of high and low voltage reset are due to the special design of the chip

Best regards

Zhao

[petervlna]

Hello,

May I ask if the different manifestations of high and low voltage reset are due to the special design of the chip

I do not understand this questions.

You can configure interrupt on LVD or HVD supported flags:

But 5.8V will not reset

But why it should reset? High voltage will not cause device malfunction like low voltage.

1* - 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.

You can even run it at 7V.

Please respect the datasheet absolute max rating.

Best regards,

Peter

[Zhaohguanyu]

Hello Peter
Thank you for your reply Sorry, I might not have made my question clear before

When I enable the High-Voltage Detect Interrupt Enable (HVDIE), the debugger can halt inside the interrupt service routine at ≈ 5.8 V.
However, when I enable the Low-Voltage Detect Interrupt Enable (LVDIE), the MCU resets immediately at ≈ 2.8 V and I never reach the ISR.
Even with LVDIE disabled, the device still resets at the same 2.8 V threshold.
Is this behavior (no ISR entry and immediate reset at the low-voltage trip point) the intended operation, or should the LVD be able to execute its interrupt handler before resetting?

Best regards
Zhao

[petervlna]

Hello,

Even with LVDIE disabled, the device still resets at the same 2.8 V threshold.
Is this behavior (no ISR entry and immediate reset at the low-voltage trip point) the intended operation, or should the LVD be able to execute its interrupt handler before resetting?

This is expected behavior. I am not sure how it is implemnted on S32K3 but usually there are 2 sets of LVDs. One that trigger interrupt and one that triggered hard reset when voltage drops there.

That would be your 2.8V. As there is no point for interrupt. as your memories, core execution, register settings may already be corrupt. And you wont do anything in interrupt due to malfunction.

Best regards,

Peter

[Zhaohguanyu]

Hello
I slowly lower VDD from 5 V.
I expect the interrupt-level LVD to fire at some higher threshold (3 V, 3.2 V, whatever is configured) so that my ISR can run before the supply becomes critical, and only later, when the rail finally reaches the 2.8 V hard-reset trip point, should the MCU reset.

For the reset-level LVD (the one that trips at 2.8 V in my test), does the data-sheet list any user-visible trim bits, register fields, or factory-configurable options that let me move its threshold, or is it a fixed, non-maskable voltage monitor?
For the interrupt-level LVD (the one that should fire earlier, around 3 V–4 V), does the manual give programmable register fields (e.g. LVDVSEL, LVDSEL, or similar) that let me select its exact trip point, and if so what are the allowed steps/min-max range?
If both thresholds are documented, please quote the register names and bit-fields; if one of them is hard-wired, please state which one is fixed

Best regards,
Zhao

[petervlna]

Hello,

For the reset-level LVD (the one that trips at 2.8 V in my test), does the data-sheet list any user-visible trim bits, register fields, or factory-configurable options that let me move its threshold, or is it a fixed, non-maskable voltage monitor?

it is not visible to customer. Besides each chip has its own calibration values for regulators trimmed in NXP factory to satisfy specification.

For the interrupt-level LVD (the one that should fire earlier, around 3 V–4 V), does the manual give programmable register fields (e.g. LVDVSEL, LVDSEL, or similar) that let me select its exact trip point, and if so what are the allowed steps/min-max range?

The interrupt-level LVD on the S32K3 (PMC‑LVDSC1) does not provide programmable threshold fields like LVDVSEL or LVDSEL. Its trip point is factory-calibrated and not adjustable via software.

If both thresholds are documented, please quote the register names and bit-fields; if one of them is hard-wired, please state which one is fixed

Both are not user accessible. Both trip points are hard-wired.

Best regards,

Peter

[ljingwang]

您好
以HVD为例，电压调节至6V，根据MCAL配置项的描述，PMC中断会在HVDAF寄存器被置1时触发，我在触发POWER_IP_E_ISR_HIGH_VOLTAGE事件后在McuErrorIsrNotification回调函数中执行了复位操作，复位后看到HVDAF寄存器被清0，但不会再被置1，所以PMC中断只会触发一次，只执行了一次复位操作，请问这个现象是正常的吗
顺祝商祺
liao