S32K312 - AIPS_PLAT_CLK and unhandled exception - bus error

[DGB]

Hi, I'm using S32K312 MCU along with RTD 2.0.1 and I faced quite strange issue. I'm using "Option B" clocking which means CORE_CLK is derived from PLL and clocked to 120Mhz and AIPS_PLAT_CLK is set to 60Mhz. In such configuration everything is working as it should. But when I change divider of AIPS_PLAT_CLK and set it to 40Mhz I'm receiving bus error unhandled exception during SWT initialization (late state, somewhere after soft lock setting). Since it's IMPRECISE exception, it's not so obvious what is causing it. According to reference manual SWT peripheral is not related in any way with AIPS_PLAT_CLK that is why I don't understand this issue. Is there any connection between SWT and AIPS_PLAT_CLK? Is there any restriction in terms of setting 40Mhz clock for AIPS_PLAT_CLK?

[davidtosenovjan]

It is needed to keep ratio between frequency domains as stated in specified clock Option.

If CORE_CLK is 120MHz then AIPS_PLAT_CLK must be 60MHz. It is mandatory

[DGB]

I see, ok this seems to be fair, but in RM I saw only the statement that AIPS_PLAT_CLK must have equal or less clock value than CORE_CLK. Anyway if I would like to downclock CORE_CLK to eg. 40 Mhz during the runtime for any reason I have to keep this ratio or I can have AIPS_PLAT_CLK also clocked to 40Mhz? I tested such switching to 60Mhz and seems it's working properly, so I managed to downclock CORE_CLK to 60Mhz and AIPS_PLAT as well to 60Mhz, without keeping the ratio. In which situation it's required to keep the ratio between the clocks?

[davidtosenovjan]

I just found where it is stated. See screenshot below:

[DGB]

Ok, so from this statement it's obvious that ratio between clocks shall be kept as long as it's according to example clock configuration. But what about mentioned above case, that we downclock CORE_CLK to 60Mhz, does AIPS_PLAT_CLK also can be clocked to 60Mhz or the ratio shall be kept? The same situation with CORE_CLK clocked to 40Mhz, what value of AIPS_PLAT_CLK is possible to be compliant with RM?

[davidtosenovjan]

Such configuration fits to Option F.

[DGB]

Hi, not really fits. My above example consider CORE_CLK to be downclocked during the runtime to 60Mhz or 40Mhz, with same clock value for AIPS_PLAT_CLK (respectively 60Mhz or 40Mhz). As I checked on HW seems it's working, but I would like to have confirmation, that it can be supported by MCU?

In addition since clocks configurations described in RM are as it's stated "Clocking use case example", they're only examples, and shouldn't limit the possibilities to few options. At least this is my understanding, correct me if I'm wrong.

[davidtosenovjan]

Do you have latest RM?

S32K3xx Reference Manual, Rev. 8, 01/2024

Clocking options are no longer marked as "examples" as these are requirements.

Specified frequencies of particular Option X are maximum ones but ratios between all domains must be kept as already screenshot above.

120/60 is ok for Option B
60/60 is ok, but it is Option F
40/40 should be also ok as Option F

Runtime transition between Options is not prohibited.

[DGB]

I just downloaded RM and only available version which I managed to get from nxp.com side is rev 6.1, which still has clocking options marked as example. Could you please share the link with new RM in rev 8? 

[davidtosenovjan]

https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-gener...

[DGB]

Thank you, so Option F assumes CORE_CLK to be set to 80Mhz and AIPS_PLAT_CLK also to 80Mhz, so in my case 60Mhz/60Mhz or 40Mhz/40Mhz should be ok since ratio between clocks will be preserved 1:1, correct?

In addition I noticed following statement in RM:

And In Option B for S32K312 wait states shall be disabled, does it also applies to Option F? Should WS be disabled as well despite what above notice refers?:

[davidtosenovjan]

Understandably so. The note applies to all derivatives, and not everywhere is indicated "WS disabled"

[DGB]

So according to my question WS shall be disabled for S32K312 using option F?

I have in addition two more questions:

1. Summarizing, this clocking chapter in RM describes the only proper possibilities for clocks setup, and it's allowed to manipulate clocks values (using dividers) itself as long as we keep the ratio between the clock for particular Option, correct? If so in Option F I'm not allowed to have 60Mhz/60Mhz for CORE_CLK and AIPS_PLAT_CLK since PLL is set to 80Mhz. Does it mean that it's also ok to manipulate PLL settings? At the end I would like to understand which clocks settings I can change and which I should derived from RM?

2. In RM in rev 9 for Option F and S32K312 MCU CORE_CLK is clocked to 80Mhz but AIPS_PLAT_CLK to 60Mhz which is not feasible since both are derived from common PLL (80Mhz), is it a bug in the documentation or I'm missing something?:

[davidtosenovjan]

WS is supposed to be disabled for S32K312 using option F.

1) All clock domain needs to be changed accordingly. Including HSE_CLK

 and others.

PLL settings you may change how you need it to create particular clocking scheme. Yes, you may change it to 60MHz.

2) Yes, it seems to be wrong in the RM as it shows

MC_CGM.MUX_0_DC_0[DIV] = (000b) = 80MHz and
MC_CGM.MUX_0_DC_1[DIV] = (000b) = 60MHz

what's obvious nonsense as both are coming from same source.

It should be either 80/40 or 60/30.

Let me check with factory. Thanks for highlighting of the issue.

[DGB]

Ok, seems to be more clear now. I have last example to verify, so it would be ok to have PLL set on 120Mhz (like in Option B) but CORE_CLK/AIPS_PLAT_CLK set to 40Mhz and AIPS_SLOW_CLK/DCM_CLK set to 30Mhz? 

I'm asking because in Option B the AIPS_SLOW_CLK and DCM_CLK is set to 30Mhz and during downclocking to Option F (40Mhz for CORE_CLK/AIPS_PLAT_CLK ) ratio between AIPS_PLAT_CLK and AIPS_SLOW_CLK will be not respected, it such approach acceptable? Which clock ratios are mandatory to keep?

[davidtosenovjan]

Now you can download Rev.9 of RM and frequencies are corrected to 80/40MHz. Hoping now it is clear.

https://www.nxp.com/webapp/Download?colCode=S32K3XXRM