S32K310 SPI ERROR

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S32K310 SPI ERROR

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Embedded_novice
Contributor III

当我使用S32K310进行SPI通信时,出现了两个问题:(我是用的MCAL版本为SW32K3_S32M27x_RTD_R21-11_5.0.0,EB版本为29.0)

1.我配置CLK在空闲时为高电平,但是当我在调用SPI_Init初始化后,CLK变成了低电平?这是为什么,而且我觉得这会影响到我的下一个问题。(在执行Base->CFGR1 = PhyUnitConfigPtr->Cfgr1;后被拉低)SPI_ERROR.pngstep1.png

2.我尝试发送1~10的数字,但是获取到的SPI波形却出现了错误,并且在CS拉高后,MOSI的电平也没有回到高电平transfer.pngstep2.png

请问有什么排查方向可以提供给我吗?感谢帮助!

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Embedded_novice 

Regarding the first image, occasionally you might observe pulses on the SCK and MOSI pins. These pulses are caused by the CPOL/CPHA and polarity configuration. When the DataShiftEdge is leading and a new transfer begins, the SPI hardware switches the data line polarity to pre-shift the first bit, which generates this pulse. In non-continuous transfers, the SPI hardware performs this switching operation for each data width (SpiDataWidth) bit. However, in continuous transfers, this switching operation occurs only once at the start.

Additionally, when using GPIO to simulate the SPI's CS with CPOL set to 1, the low-level pulse generated on the SCK pin each time is due to the first workaround for ERR050456, which involves resetting the LPSPI module. If the second workaround is selected (by defining the macros ERR_IPV_LPSPIV2_E050456 and ERR_IPV_LPSPIV2_E050456_2ND_SOLUTION), the low-level pulse should not appear.

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Embedded_novice 

Are you using a custom board or the S32K31XEVB-Q100? Could you please share your configurations? I would like to replicate the situation on my side to help identify the cause of this behavior.

Additionally, we have observed that other peripherals are enabled. Could you try testing with a simple application that only uses the SPI? This will help verify whether something else in the application might be affecting the behavior.

 

BR, VaneB

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Embedded_novice
Contributor III

@VaneB 我需要补充一些信息给你参考。

在上一次中我没有使用硬件SPI的自动CS,而是在JOB回调函数中手动使能和失能CS引脚。下面的图是我使用硬件SPI的自动CS得到的结果,数据发送恢复了正常。

首次通信:First.png

第二次通信Second.png

我在这里看到在每次通信结束,CS失能后,MOSI一直处于低电平状态,直到下一次通信开始前CLK会有一个脉冲使MOSI恢复至高电平(红框位置)。

但是如果我是用JOB回调手动控制CS的使能,这会使得CS的使能提前到红框位置前,CLK的重置行为会导致我将其识别为通信起始,这样就会造成通信错误。

我的问题是我该如何取消这种重置行为?

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Embedded_novice 

Regarding the first image, occasionally you might observe pulses on the SCK and MOSI pins. These pulses are caused by the CPOL/CPHA and polarity configuration. When the DataShiftEdge is leading and a new transfer begins, the SPI hardware switches the data line polarity to pre-shift the first bit, which generates this pulse. In non-continuous transfers, the SPI hardware performs this switching operation for each data width (SpiDataWidth) bit. However, in continuous transfers, this switching operation occurs only once at the start.

Additionally, when using GPIO to simulate the SPI's CS with CPOL set to 1, the low-level pulse generated on the SCK pin each time is due to the first workaround for ERR050456, which involves resetting the LPSPI module. If the second workaround is selected (by defining the macros ERR_IPV_LPSPIV2_E050456 and ERR_IPV_LPSPIV2_E050456_2ND_SOLUTION), the low-level pulse should not appear.

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Embedded_novice
Contributor III

@VaneB 

我使用的是自己绘制的PCB硬件,MCU封装是S32K310_48LQFP。我可以将我的EB工程打包给您参考。此外我会尝试关闭其他外设,仅使用SPI进行验证。

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