S32K3 Noncorrectable Error of FLEXCAN

[CoinFish]

I am porting the CAN diagnostic communication protocol stack for mpc56xx to the S32K3 platform. I am currently modifying the CAN driver layer. I am not using the official CAN driver, but modifying the original driver.

I initialized can2 and can3. Shorted them to form a CAN network. CAN2 sends 0x262 and receives 0x263, CAN3 sends 0x263 and receives 0x262. The terminal resistors are also configured correctly. The problem is that after CAN2 and CAN3 successfully sent a message, both triggered a noncorrectable error and entered freeze mode.

The MCR[MAXMB]for can2 and can3 are 0x3f and 0x1f respectively. I did not initialize all MB of RAM space, but only MAXMB amount of RAM.

When the error happened:

for can2: RERRAR[ERRADDR]=0X0548; RERRAR[SAID]=0X1; RERRAR[NCE]=0X1;  ERRSR[FANCEIF] = 1

for can3: RERRAR[ERRADDR]=0X02C8; RERRAR[SAID]=0X1; RERRAR[NCE]=0X1;  ERRSR[FANCEIF] = 1

Some other information：

a. if can2 and can3 are not short-circuited, messages can be sent and received normally.

b. If not only initialize maxmb of RAM space, but all MB ram space, the noncorrectable error will not happen, send and receive normally. (about this, I guess the flexcan accessed the uninitialized RAM space, but maxmb has limited the access location of flexcan. I don't know why this happened.)

If any additional information is needed please let me know, this problem has been bothering me for over a week now.

[PetrS]

Hi,

S32K3 FlexCAN supports detection and correction of errors in memory read accesses. This ECC mechanism is enabled by default. In such case you should initialize necessary memory spaces before module is put in Normal mode.

So besides MB area you also need to initialize some other registers , including RXFIR, RXxxMASK, Tx_SMB, Rx_SMB, as shown in below offsets

/* init the area 0x0A80~0xA9F; RXFIR_0~RXFIR_5 + Reserved space*/
/* init the area 0x0AA0~0xAAF: RXMGMASK, RXFGMASK, RX14MASK, RX15MASK, */
/* init the area 0x0AB0~0xADF: Tx_SMB, Rx_SMB0, Rx_SMB1, */

Or disable ECC mechanism at all by setting MECR[ECCDIS] bit. See more in chapter 73.3.15 Detection and correction of memory errors.

BR, Petr

[CoinFish]

Thanks Petr, I did notice the NOTE, but i still have 3 confusions.

1. I couldn't find the memory location of the Tx_SMB, Rx_SMB0, Rx_SMB1 you listed above. besides the RXMGMASK, RXFGMASK, RX14MASK, RX15MASK are not in 0X0AA0~0XAAF and RXFIR_0~RXFIR_5 are not in 0x0A80~0xA9F in my manual. and it seems that RXFIR_0~RXFIR_5 don't even need to be initialized.

2. I know that certain memory and registers need to be initialized, but there seems to be no clear instructions for initialization in the manual. What i did is, set CTRL2[WRMFRZ] = 1; clear the memory and registers that need to be initialized to be 0 and then set  CTRL2[WRMFRZ] = 0; am i right? and what is the principle behind it?

3. Why the FLEXCAN reads more memories than i set? I thought MAXMB limits the range of FLEXCAN reads.

Can you explain it more clearly and in detail? Thanks

[PetrS]

Hi,

1) those addresses are shown in ERRIAR register chapter (table 522)
2) yes, a CTRL2[WRMFRZ] usage is right. A reason for initialization is to update parity bits in memory properly. FlexCAN supports detection and correction of errors in memory read accesses. Each byte of FlexCAN memory is associated with five parity bits. When a read access is performed, the parity bits are used to calculate a syndrome, which indicates the error in each byte.
3) yes, module should not use space outside area specified by MAXMB. But hard to say more without knowing full config and code used.

BR, Petr