Hi Yusup,
On Cortex‑M7, there are D‑Cache and I‑Cache that operate on cacheable memory regions when enabled.
Whether a memory region is cacheable or not is configured in the core’s MPU.
In an S32DS IDE project, please refer to the linker file and system.c, where the MPU is configured and the I‑Cache and D‑Cache are enabled. Some memory regions are configured as cacheable, while others are configured as non‑cacheable.
1. Yes, it is possible. However, I do not see any reason to disable the cache. You would need to configure the regions where the flash driver operates as non‑cacheable, or disable the cache entirely.
2. The driver takes care of cleaning the cache if Mem Clean Cache After Load Access Code is set to 1. If the SRAM region where you copy the driver code is configured as non‑cacheable, you can set Mem Clean Cache After Load Access Code to 0.
3. Nothing special in this context. In general:
Pros: Cache greatly improves performance and reduces CPU stalls by keeping frequently used data and instructions close to the core.
Cons: Cache adds complexity and can cause data coherency issues.
4. Yes, it is good practice to clean and disable the cache. The startup code of the application will then reconfigure the MPU and re‑enable the cache. Also, refer to the S32K3xx Reference Manual, Section 3.8, Serialization of Memory Operations.
Regards,
Daniel