S32K3 Clock Switching Flowchart

[kscz]

The S32K3 reference manual section 25.4.1.2 has the following flowchart:

 And the MUX_0_CSC register description has this diagram in section 25.5.6:

 What is "MUX_n_CSC[CG]" referring to in the register??

[PetrS · Accepted solution]

Hi,

The MC_CGM provides two types of clock multiplexers:
- Hardware‑controlled clock multiplexers, and
- Software‑controlled clock multiplexers.

Figure 124 illustrates the clock‑switching flow for software‑controlled multiplexers only, using either the synchronous/graceful clock gate bit (MUX_n_CSC[CG]) or the forced clock gate bit (MUX_n_CSC[FCG]).

The CG/FCG bits are available only on software‑controlled multiplexers, such as MUX_5_CSC, MUX_6_CSC, etc.

To determine whether a specific multiplexer is hardware‑ or software‑controlled, refer to the MUX_n_CSC register description in the reference manual.

BR, Petr

[kscz]

Yeah, I see this now. I was confused because I assumed that "software-controlled" meant that the software that I was writing controlled it, but both types of clock muxes have software initiate the control.