After several tests, it appears to me that all LPIT channels on the S32K144 map to a single interrupt LPIT0_Ch0_IRQn with NVIC ID# 48. That is to say an overflow of the channel 1,2, and 3 of the LPIT with the interrupt enabled will trigger NVIC interrupt 48.
This is consistent with a comment made previously on this forum by Lukas Zadrapa in October 2016:Clock Cofiguration for TIMER
Hi,
I just realized that all LPIT channels are assigned to single interrupt vector IRQ 48.
...
It looks like the documentation needs to be updated.
This is inconsistent with the latest reference manual, S32K1xx_DMA_Interrupt_mapping, and header S32K144.h. See below for a fragment from the header (Line 327):
LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */
LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */
LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */
LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */
Is this expected behavior for the S32K1xx microprocessors? Is the recommended workaround to use the "Ch0" interrupt to check the LPIT status registers and call the appropriate interrupt service routine? Will there be an update to the documentation?
Thank you for your help,
Paul
