[S32K1x] Regarding the calculation of the total conversion time of ADC

[GavinLi1]

Dear NXP Experts,

I'm confused about the conversion time of ADC for S32K1x.

In the data sheet, I can get the f_ADC conversion frequency is 928Ksps under the typcal working frequency - 40Mhz.

The point 7 mentions the minimum sampling time is 275ns which is 11 Adc clock.

However, I can't get  the 928Ksps result based on the calculation method in the RM shows as below:

Assum the adc is in 12-bit mode
ADC TOTAL CONVERSION TIME = 11( Sample Phase Time) + 1 ( Hold Phase) + 28 (12bit mode) + 10 (5 ADC cycles + 5 bus clock cycles) = 50 Adc clock  

The result is not match with 928Ksps in the data sheet.

I know there exist some missmatch for my understanding, so could you kindly point where is wrong for my understanding?

Thanks in advance,

Gavin

[PetrS]

Hi,

as the DS shows continuous conversion values, then equation without time adder should be used
ADC TOTAL CONVERSION TIME = Sample Phase Time (set by SMPLTS + 1) + Hold
Phase (1 ADC Cycle) + Compare Phase Time (8-bit Mode = 20 ADC Cycles, 10-bit
Mode = 24 ADC Cycles, 12-bit Mode = 28 ADC Cycles)

Then assuming min sample time (275ns) only 1160Ksps@50Mhz is correct 

ADC TOTAL CONVERSION TIME = 14( Sample Phase Time) + 1 ( Hold Phase) + 28 (12bit mode) = 43 ADC cycles .... 0.86us ~ 1162Ksps

Rest is probably calculated with same setting, using 43 ADC cycles.

BR, Petr

[GavinLi1]

Hi Petr,
Thanks for your feeback!

Two more questions:
1. If assuming the ADC works at 40Mhz.
The sample time 275 ns is 11 clock.
ADC TOTAL CONVERSION TIME = 11( Sample Phase Time) + 1 ( Hold Phase) + 28 (12bit mode) = 40 ADC cycles ... 1Msps. However, the DS shows is 928Ksps.
My question is ：The DS gives the result as 928Ksps. Is it for conservative considerations or are there other reasons?

2. How to set the sample phase time in the reister if I want to get shorter adc conversion time? Any advision?

Many thanks,
Gavin

[PetrS]

Hi,

1) as I wrote, value is probably get using the same config as for 50MHz, that is 14 sample times, in total 43 ADC clocks. Thus you get 40MHz/43 ~ 930Ksps. Minimum conversion time (max conv freq) is the one you gave, 1Mbps 

2) calculate minimum (SMPLTS+1) with respect of the minimum sampling time 275ns. But you did it, assuming 40Mhz ADC clock it is 11  

BR, Petr

[GavinLi1]

Hello Petr,
Thanks!
About Q2, I'm sorry I didn't make it clear in last post.
Regarding the minimum sampling time, what are the factors that determine it? For example, if the adc uses resistors whose resistance values are relatively large, such as several tens of kilo - ohms, maybe the 275 ns is not ok ? If not, how to set the minimum sampling time for different cases?

[PetrS]

Hi,

yes, external circuitry plays important role, user should have source impedance a low as possible. For higher values, there will be a need to extent sampling time so the sample capacitor charging will settle properly.
For a deeper explanation on how to design the external RC acquisition circuit and selection of components, see application note AN4373 (https://www.nxp.com/docs/en/application-note/AN4373.pdf). Although the document refers to different MCUs, the ADC module in S32K1xx shares the same basic architecture, so the theory is also applicable.

BR, Petr