S32K148 - SAI TX overflows

[jakub_mielczare]

Hello,

Is there any way to check if there are overflows on SAI0 TX FIFOs when DMA is feeding SAI?

The S32K148 Reference Manual specifies how to check if there was underrun, but I could not find similar interrupt for overflow. I would need this information as soon as overflow happens.

Thank you,

Jakub

[lukaszadrapa]

Hi,

TX FIFO can underrun, RX FIFO can overflow. But TX FIFO can't overflow and RX FIFO can't underrun.

If DMA is used for TX FIFO and there's no empty space in the FIFO, the DMA request is simply not asserted. It's asserted only when the FIFO is not full.

Regards,

Lukas

[jakub_mielczare]

Hi Lukas,

Can TX FIFO overflow, when e.g. watermark is set to 1 and DMA transfer is set to 2x 4samples (each sample is 32-bit).

In this case DMA request would be generated by SAI when there is 1 word left in FIFO? Can DMA write 8 words before the last 1 sample leaves FIFO?

Thanks,

Jakub

[lukaszadrapa]

Hi,

It means you have to configure the DMA in a way that it cannot happen.

Regards,

Lukas

[jakub_mielczare]

Hi,

Is there any way to diagnose, that such condition has happened, i.e. transmit FIFO write was ignored, because the FIFO was full?

Regards,

Jakub

[jakub_mielczare]

Hello,

Is there any update for this thread?

Regards,

Jakub

[lukaszadrapa]

Hi Jakub,

sorry, I somehow missed that question.

No, it's simply ignored. It's user responsibility to ensure that full FIFO is not written. If DMA is not used, it's necessary to confirm before each write that FIFO is not full. If DMA is used then DMA descriptor must be configured in a way that only one sample is written to FIFO per one HW request. Then it is ensured that full FIFO will not be written again because there will be no HW trigger in this case.

In other words, it's necessary to avoid this situation, not to handle the consequences.

Regards,

Lukas

[jakub_mielczare]

Hi Lukas,

Thank you for the answer.

Regards,

Jakub