Project Brief Introduction:
1. Using S32K146 MCU;
2. Using many MCU peripherals, such as UART(BR: 230000bps), CAN, I2C, GPIO, LPIT, LPTMR, FTM(2 modules, 12 channels IC, ) etc, and we also use FreeRTOS.
3. All of peripherals above but GPIO using interrupt mode.
1. Data size on UART is about 9KB/s, we configure UART interrupt every byte, so too many interrupts performed and our application functions will be affected.
2. Now I want to use DMA to take over UART TX interrupts firstly, but I don't know whether I can sperate the UART communication(TX/RX) and use DMA on only one direction.
3. If answer for 2 is yes, then may I use SDK to implement this(currently, we use SDK to configure the UART module)? May I know the steps?
4. If answer for 2 is no, then do you have any other suggestion which can reduce my interrupts obviously.
2. The LPUART allows to use DMA only for the transmitter.
3. No, the LPUART SDK driver can be used either in Interrupt or DMA mode.
4. The FIFO WATER marks can be used (FIFO, WATER).
But the SDK driver does no use it, TXWATER = RXWATER = 0.
Thank you so much for your answer.
for question 3, I cannot understand clearly.
You mean I cannot implement only UART TX use DMA mode with current SDK?
If so, is it possible for me to implement by modify current SDK? What should I do?
Yes, it is not possible to use DMA only for the transmitter (LPUART TX) with the SDK LPUART driver.
There is no simple modification of the driver that you can do.
Why you don't use DMA for both the transmitter and the receiver?
We have a UART communication protocol, and communication frames length are not fixed value.
If I use DMA for UART reception, DMA will transfer communication bytes only one every time, currently I don't know how to increase the transfer efficiency.
One more question, I tried UART transmission with DMA, but I found a problem: My transmission success ratio only about 60%.
Picture above show you that I pack my data and call function interface "LPUART_DRV_SendDataBlocking" for transmission.
As shown in picture, I use default source code in SDK. I wonder how to increase the transfer success ratio.
Hi Xiaoyu, for your concern that using UART Rx receiving not fixed-length value. Below is a method suggested using DMA+ UART RX IDLE interrupt. For example, setting DMA BITER = 100, which means every 100 bytes received a DMA complete IRQ will be triggered. Set a counter ++ in the DMA complete callback, calculate the rest bytes in the UART RX IDLE callback by reading the CITER register of DMA, and take out the (100-CITER bytes) length of data. When you are receiving 770 bytes of data, 7 times of DMA complete callback will be called, so the counter is 7. When RX IDLE callback is called(Which means all frames are sent), CITER should be 30. And only 7+1=8 times of IRQ occurred.
In my ECU, my MCU will communication with SOC chip with UART, and both Tx and Rx frames will observe the same communication protocol.
MCU will send frames to SOC according to task need. But currently, when I use send interface which mentioned above to send my frames, about 60% of them(Tx frames) are transferred failed. Which means only 40% of my Tx-Frames are send successfully. This is my success ratio.
For problem described above, I guess that is because of the 5th parameter of interface "EDMA_DRV_ConfigMultiBlockTransfer". Currently, it is filled with "EDMA_TRANSFER_SIZE_1B", it is because of the byte width of DATA register of LPUART. But I think it is too slow that DMA will transfer only 1 byte every time. Can it be values other than "EDMA_TRANSFER_SIZE_1B"? How to configure?
Thank you ~~
As it was already discussed, the LPUART – DMA SDK implementation does not use LPUART FIFO, so, only the EDMA_TRANSFER_SIZE_1B can be used.
But the EDMA_TRANSFER_SIZE_1B parameter should not cause these issues.
Once the DMA transfer starts, it transfers one byte per a LPUART request, but it should not fail to transfer them.
What is the return status of the LPUART_DRV_SendDataBlocking() function?
Does it return TIMEOUT or any other error message?
Do you use other DMA channels with higher priorities?