Dears
We encounter an issue when we do EMC test to S32K146, S32k146 can't Enter Freeze Mode and MCU firmware always stop at the while loop here:
in void FLEXCAN_EnterFreezeMode(CAN_Type * base), in the "flexcan_hw_access.c". SDK version we now use is RTM 3.0.0.
Compare to SDK RTM 4.0.1 we found there added much more steps than RTM 3.0.0.
My question is:
1. If we update the SDK to RTM 4.0.1 can this issue will not exist?
2. Because our project will SOP soon, change SDK is not possible, how can we do to avoid stopping at while enter the FreezeMode base on the SDK 3.0.0?
SDK RTM 4.0.1 enter Freeze Mode function:
/*FUNCTION**********************************************************************
*
* Function Name : FLEXCAN_EnterFreezeMode
* Description : Enter the freeze mode.
*
*END**************************************************************************/
void FLEXCAN_EnterFreezeMode(CAN_Type * base)
{
bool enabled = false;
base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
if (((base->MCR & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT) == 0U)
{
enabled = true;
}
else
{
base->MCR &= ~CAN_MCR_MDIS_MASK;
}
#if defined(ERRATA_E9595)
/* Check Low-Power Mode Acknowledge Cleared */
while (((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) == 1U) {}
/* Check if is a Bus-Off Error corresponding to 1x */
if ((((base->ESR1 & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT) & 2U) != 0U)
{
/* Save registers before Soft Reset */
uint32_t tempIMSK[2],tempMCR;
tempIMSK[0] = base->IMASK1;
tempIMSK[1] = base->IMASK2;
tempMCR = base->MCR;
/* Soft Reset FlexCan */
base->MCR |= CAN_MCR_SOFTRST(1U);
while (((base->MCR & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT) != 0U) {}
/* Restore registers after Soft Reset */
base->IMASK1 = tempIMSK[0];
base->IMASK2 = tempIMSK[1];
base->MCR = tempMCR;
}
else
{
base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
}
#endif
base->TIMER = 0U;
uint32_t aux = 0U;
#if FEATURE_CAN_HAS_FD
/* MCR[FDEN] was reset to 0, wait for timeout */
if (!FLEXCAN_IsFDEnabled(base))
{
while (!FLEXCAN_GetFreezeMode(base) && (aux < 180U))
{
/* Wait until finish counting 180 bit times and exit*/
aux = (uint32_t)base->TIMER;
}
}
else
{
while (!FLEXCAN_GetFreezeMode(base) && (aux < 730U))
{
/* Wait until finish counting 730 bit times and exit*/
aux = (uint32_t)base->TIMER;
}
}
#else
while (!FLEXCAN_GetFreezeMode(base) && (aux < 180U))
{
/* Wait until finish counting 180 bit times and exit*/
aux = (uint32_t)base->TIMER;
}
#endif /* FEATURE_CAN_HAS_FD */
if (((base->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) == 0U)
{
/* Save registers before Soft Reset */
uint32_t tempIMSK1, tempMCR;
/* Save IMASK1 value */
tempIMSK1 = base->IMASK1;
#if FEATURE_CAN_MAX_MB_NUM > 32U
uint32_t tempIMSK2 = 0U;
if (FLEXCAN_GetMaxMbNum(base) > 32U)
{
/* Save IMASK2 value */
tempIMSK2 = base->IMASK2;
}
#endif
#if FEATURE_CAN_MAX_MB_NUM > 64U
uint32_t tempIMSK3 = 0U;
if (FLEXCAN_GetMaxMbNum(base) > 64U)
{
/* Save IMASK3 value */
tempIMSK3 = base->IMASK3;
}
#endif
/* Save MCR value */
tempMCR = base->MCR;
/* Soft Reset FlexCan */
base->MCR |= CAN_MCR_SOFTRST(1U);
while (((base->MCR & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT) != 0U) {}
/* Restore IMASK1 value */
base->IMASK1 = tempIMSK1;
#if FEATURE_CAN_MAX_MB_NUM > 32U
if (FLEXCAN_GetMaxMbNum(base) > 32U)
{
/* Restore IMASK2 value */
base->IMASK2 = tempIMSK2;
}
#endif
#if FEATURE_CAN_MAX_MB_NUM > 64U
if (FLEXCAN_GetMaxMbNum(base) > 64U)
{
/* Restore IMASK3 value */
base->IMASK3 = tempIMSK3;
}
#endif
/* Restore MCR value */
base->MCR = tempMCR;
}
if (false == enabled)
{
base->MCR |= CAN_MCR_MDIS_MASK;
/* Wait until disable mode acknowledged */
while (((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) == 0U) {}
}
}
