S32K144W SPI SCLK ，delay after four bytes

[tyty697]

This is my SPI1 config屏幕截图 2025-09-24 184848.png

I will transfer 40 bytes

LPSPI_DRV_MasterTransferBlocking(INST_LPSPI_1, config_arr, rx_buff, 40, OSIF_WAIT_FOREVER);

This is wave of SCLK.I wish SCLK is contious.TDR and RDR is 32 bits,does it have anything to do with it?What can I do to slove this problem?

9749e2626aec43a7b43e1a9b7a968e8a.png

[PavelL]

Hello @tyty697 ,

Thank you for sharing the configuration and waveform details.

Based on your setup, the observed delay in SCLK after every 4 bytes is likely caused by the PCS continuous setting being disabled. When this option is unchecked, the chip select (PCS) signal is deasserted between frames, which introduces gaps in the SCLK waveform.

To achieve a continuous SCLK during the entire 40-byte transfer, we recommend enabling the PCS continuous option in your LPSPI master configuration. This will keep PCS asserted throughout the transfer and eliminate the inter-frame delays.

If your SPI slave supports wider frame sizes, you may increase the Bits/frame setting (e.g., to 16 or 32) to reduce the number of frames and potentially eliminate the gaps in SCLK caused by PCS toggling or FIFO refill latency.

Additionally, consider using DMA-based transfer instead of the blocking interrupt-based API. DMA can help maintain a smoother data flow and reduce latency between FIFO refills.

For future measurements, we kindly ask you to also include the PCS signal in the waveform capture. This will help us better understand the timing behavior and interactions between PCS and SCLK.

Best regards,

Pavel

[tyty697]

Now I clicked pcs contious,this is spi config

屏幕截图 2025-09-25 090321.png

Set PCSSCLK and sclkpcs 1,1

 

LPSPI_DRV_MasterSetDelay(INST_LPSPI_1, 1, 1, 1);

PCS and sclk waveform shows here

 1d05c04a3f364e20b74d4babbc6c6396.png9924e180-8b6c-4417-9cff-3158b9148dee.png

Delay after four bytes too. I see this function used in the spi IRQHandler when TX Data Flag

/*!

 * @brief Fill up the TX FIFO with data.

 * This function fills up the TX FIFO with data based on the bytes/frame.

 * This is not a public API as it is called from other driver functions.

 */

void LPSPI_DRV_FillupTxBuffer(uint32_t instance)

{

    /* Instantiate local variable of type dspi_master_state_t and point to global state. */

    lpspi_state_t * lpspiState = g_lpspiStatePtr[instance];

    LPSPI_Type *base = g_lpspiBase[instance];

    uint32_t wordToSend = 0;

    uint16_t numOfBytes;

    uint8_t availableSpace = (uint8_t)(lpspiState->fifoSize - (uint8_t)LPSPI_ReadTxCount(base));

    /* Fill the TX buffer. */

    while(availableSpace != 0U)

    {

        if (lpspiState->isPcsContinuous == true)

        {

            if(lpspiState->txCount == 1U)

            {

                /* Disable continuous PCS */

                LPSPI_ClearContCBit(base);

                lpspiState->txCount  = 0U;

                break;

            }

        }

        /* Get the number of bytes which can be written in a single 32 bits word. */

        if ((lpspiState->bytesPerFrame - lpspiState->txFrameCnt) <= (uint16_t)4)

        {

            numOfBytes = (uint16_t)(lpspiState->bytesPerFrame - lpspiState->txFrameCnt);

        }

        else

        {

            numOfBytes = 4U;

        }

        wordToSend = 0;

        if (lpspiState->txBuff != NULL)

        {

switch(lpspiState->bytesPerFrame)

{

case 1:

wordToSend = *((const uint8_t *)(lpspiState->txBuff));

lpspiState->txBuff += sizeof(uint8_t);

break;

case 2:

wordToSend = *((const uint16_t *)(lpspiState->txBuff));

lpspiState->txBuff += sizeof(uint16_t);

break;

default:

wordToSend = *((const uint32_t *)(lpspiState->txBuff));

lpspiState->txBuff += sizeof(uint32_t);

break;

}

lpspiState->txFrameCnt = (uint16_t)((lpspiState->txFrameCnt + numOfBytes) % lpspiState->bytesPerFrame);

        }

        LPSPI_WriteData(base, wordToSend);

        /* Update internal variable used in transmission. */

        lpspiState->txCount = (uint16_t)(lpspiState->txCount - numOfBytes);

        /* Verify if all bytes were send. */

        if (lpspiState->txCount == 0U)

        {

            break;

        }

    availableSpace = (uint8_t)(availableSpace - 1U);

    }

}

144w's fifosize is 4, maybe this reason?

[PavelL]

Hello @tyty697 ,

Thank you for the update and the waveform.

Yes, you are correct - the FIFO size of 4 words on S32K144W is indeed related to the observed SCLK burst behavior. Each burst corresponds to the driver filling the FIFO with up to 4 bytes (given Bits/frame = 8), and the delay between bursts is caused by the refill process in interrupt mode.

To reduce these gaps, we recommend either switching to DMA-based transfer or increasing the Bits/frame setting (e.g., to 16 or 32), if your SPI slave supports wider frame sizes.

Best regards,

Pavel

[tyty697]

Hello,@PaveIL

Thanks for your response,DMA has sloved this problem.But l have other problem.

l want to read six channels of ADC chip,so l use function LPSPI_DRV_MasterTransferBlocking to communicate by SPI BUS.But when l call this function contiously, There is a interval between two calls like this formwave.

66fa43ae75734e579c1e68ed7b37cda7.png

One Time I need to send 5 bytes,send 6 times to read 6 channels.If I send 30 bytes one time,ADC chip can't response right data.What can I do to decrease this interval?

[PavelL · Accepted solution]

Hello @tyty697 ,

Just a general hint: 

You may try switch to the non-blocking DMA API (LPSPI_DRV_MasterTransfer) and chaining the transfers without CPU intervention. This allows for near-continuous SPI communication and better timing control.

Best regards,

Pavel