S32K144 and SBC(MC33FS6500) SPI CS Problem

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S32K144 and SBC(MC33FS6500) SPI CS Problem

1,840 Views
engineer_attila
Contributor III

Hi folks, 

When communicating SPI between S32k144 and SBC (MC33FS6500), I see that the Chip Select pin is unexpectedly pulled to high while the message transmission is still in progress.
What can I do ?

Screenshot_3.png

FS65_SPI3.png

My SPI config

Screenshot_1.png

11 Replies

1,798 Views
engineer_attila
Contributor III

Hi @danielmartynek ,

As you seen, 16 clock cycle ,16 bit

This is transfer function 

Screenshot_4.png

I changed the bitcount to 32, nothing changed.

 

 

 

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1,784 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Did you really change the bitcount in the configuration of the driver?

danielmartynek_0-1675250468264.png

 

 

 

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1,776 Views
engineer_attila
Contributor III

Hi @danielmartynek , 

Our main problem is related to CS pin state inconsistency . 

We have to use 16 bit frame format in order to communicate our sensor(FS65xx) . But Sometimes CS pin logic level changed without any reason(as you seen above pictures). 

What cause this problem? How can we eliminate this CS select inconsistency

 

Best regards.

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1,771 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @engineer_attila,

I'm sorry, I misread the issue.

In this case, can you measure the bus with an analog oscilloscope?

This digital signal does not tell whether the signal goes all the way to VDD or if it is just a glitch.

Does it happen always at the time MOSI is HIGH?

 

Thanks,

Daniel

 

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1,752 Views
engineer_attila
Contributor III

Hi @danielmartynek ,

Most of the times it occurs during when MOSI was HIGH,

But sometimes this CS problem not seen alongs with transmission. 

I'm curious , is it related to MOSI?

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1,746 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi @engineer_attila,

Which pin do you use for the CS?

If the pin has the High-drive capability (GPIO-HD), is the the PCR[DSE] bit of the pin set?

 

Thanks,

BR, Daniel

 

 

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engineer_attila
Contributor III

Hi @danielmartynek ,

 

This is my pin configuration

 

Screenshot_1.pngScreenshot_2.png

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danielmartynek
NXP TechSupport
NXP TechSupport

This PTB17 does not have the GPIO-HD function.

Can you use different PCS?

Like PTB5

 

danielmartynek_1-1675682190619.png

Have you been able to measure the signal with an analog osciloscope?

Can you decrease the bitrate?

 

Thanks,

BR, Daniel

 

 

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1,499 Views
engineer_attila
Contributor III

Hi @danielmartynek , 

Sorry for late response. My colleagues will change the CS pin to GPIO-HD for next revision.

I'm curious what is the equivalent of  GPIO-HD pins for MPC5775 series?  

Best regards.

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1,491 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @engineer_attila,

Did you get rid of the glitches with this configuration? How does it look at an analog osciloscope?

 

I'm not familiar with the MPC5775 series, but I see there is a similar option in the PCR[SRC] register.

On S32K1xx, the GPIO-HD pins with PCR[DSE] = 1 have higher current capabilities and are faster.

 

danielmartynek_1-1676633241330.png

danielmartynek_2-1676633320014.png

Also, the whole LPSPI specification in the DS was taken at GPIO-HD pins (DSE = 1):

danielmartynek_3-1676633443448.png

 

Regards,

Daniel

 

 

 

 

1,814 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi @engineer_attila,

How long the transfer should be?

Can you show how you call the transfer function?

You could increase the .bitcount to 32, for example.

 

Regards,

Daniel

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