S32K144 SPI baudrate

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S32K144 SPI baudrate

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lyz
Contributor II

How do caculate S32K144 SPI Baudrate. How is computational formula?I see that in SDK. As fllow:


realBaudrate = (sourceClockInHz / (s_baudratePrescaler[prescaler] * (scaler + (uint32_t)2U)));


but, I do not understand. please tell me how is computational formula! thanks.

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VaneB
NXP TechSupport
NXP TechSupport

Hi @lyz 

The SPI baud rate is calculated as:

Baud Rate = (Functional clock / PRESCALE) / (SCKDIV+2)

PRESCALE: Configured in the Transmit Command Register (TCR).

SCKDIV: Configured in the Clock Configuration Register (CCR).

If you find the SDK implementation confusing, refer to section 2.8 of the S32K1xx Series Cookbook. It is a good starting point for understanding how to configure the LPSPI.

 

BR, VaneB

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VaneB
NXP TechSupport
NXP TechSupport

Hi @lyz 

The SPI baud rate is calculated as:

Baud Rate = (Functional clock / PRESCALE) / (SCKDIV+2)

PRESCALE: Configured in the Transmit Command Register (TCR).

SCKDIV: Configured in the Clock Configuration Register (CCR).

If you find the SDK implementation confusing, refer to section 2.8 of the S32K1xx Series Cookbook. It is a good starting point for understanding how to configure the LPSPI.

 

BR, VaneB

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lyz
Contributor II

lyz_0-1762514940762.png

Project from example config delay in SDK, as follow. Why? I do not understand:

lyz_1-1762515003416.png  

in S32K1xx Series Cookbook.lyz_2-1762515048459.png

so,

How config SCKPCS of SCK-to-PCS Delay?

How config PCSSCK of PCS-to-SCK Delay?

How config DBT of Delay Between Transfers?

 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @lyz 

The bestScaler is used to configure delay registers because these delays scale with the SPI clock. Applying a right shift by 2 (>> 2U, equivalent to dividing by 4) ensures the delay values remain proportional to the baud rate without being excessively large, providing balanced timing margins for PCS-to-SCK, SCK-to-PCS, and Delay Between Transfers.

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lyz
Contributor II

hello, @VaneB 

    Project from example config delay in SDK, as follow

lyz_0-1762742669180.png

the logic (>> 2U, equivalent to dividing by 4) refence where describe, Why?

I fell that it is diffent the logic whitch the reference of S32K-RM.pdf provide, as follow:

I do not understand!

lyz_1-1762742702023.png

What is the configuration logic, about SCKPCS / PCSSCK / and PCSSCK ? 

Please tell me.

Thank you very much!

 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @lyz 

The use of >> 2U (equivalent to dividing by 4) for delay calculations is not documented in the reference manual as a strict formula. Instead, it originates from SDK timing guidelines intended to ensure proper functionality.

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lyz
Contributor II

I understand logic in SDK code, but the logic (>> 2U, equivalent to dividing by 4) refence where describe. The reference of S32K-RM.pdf provide of the logic, as follow:

lyz_0-1762650599443.png

 

so, What is the configuration logic, about SCKPCS / PCSSCK / and PCSSCK ?

How config SCKPCS of SCK-to-PCS Delay?

How config PCSSCK of PCS-to-SCK Delay?

How config DBT of Delay Between Transfers

in detail.

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lyz
Contributor II

ok, thank you. 

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lyz
Contributor II

 I do not understand these:

The SCK period is equal to (SCKDIV+2) cycles of the LPSPI functional clock divided by the Prescaler Value TCR[PRESCALE] configuration.

realBaudrate = (sourceClockInHz / (s_baudratePrescaler[prescaler] * (scaler + (uint32_t)2U)));

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