S32K144 FLASH CACHE

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S32K144 FLASH CACHE

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arkadyosh
Contributor III

Hi,
At present I work on write to PFLASH and DFLASH memory. Im little confused about disabling flash cache. There is flash partitioning example in S32SDK_S32K14x_EAR_0.8.6 where is code disabling flash cache:

/* Disable cache to ensure that all flash operations will take effect instantly,
* this is device dependent */
#ifdef S32K144_SERIES
MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);
MSCM->OCMDR[1u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);
MSCM->OCMDR[2u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);
MSCM->OCMDR[3u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);
#endif /* S32K144_SERIES */

But in S32K-RM rev. 6 theres no bits OCM0, OCM2 for registers OCMDR[0], OCMDR[1] and any OCMx bits in OCMDr[2] and even register OCMDR[3]. OCM1 is 2bits wide, not 4bits like in axample above. Some of bits which is write in example is Reserved based on S32K-RM.

I think this code should look like this for S32K144:

#ifdef S32K144_SERIES
MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM1(0x3u);

MSCM->OCMDR[1u] |= MSCM_OCMDR_OCM1(0x3u);

#endif /* S32K144_SERIES */

Please clarify how to disable cache for memories for S32K144 0N57u.

What are advandages/disadvantages for disabling cache when write/erase PFLASH, DFLASH and should be it disabled when I want for example update firmware by my custom bootloader?

Regards,

Arkadiusz

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7 Replies

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arkadyosh
Contributor III

Hi Daniel,

Thank you for answer, but one more question, should I disable PFLASH and DFLASH cache if I want write only to DFLASH or just only DFLASH cache?

Regards,

Arkadiusz

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490 Views
assangeye
Contributor I

Hi,Arkadiusz,

Have you solved  this problem?

I found that if i put this code in my project,the time of executing every line code will be slow when i use IAR compier.

#ifdef S32K146_SERIES
MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM1(0xFu);
MSCM->OCMDR[1u] |= MSCM_OCMDR_OCM1(0xFu);
MSCM->OCMDR[2u] |= MSCM_OCMDR_OCM1(0xFu);
#endif /* S32K144_SERIES */

I really dont konw what does this code mean?  i wonder that do i have to using this code to disable cache  when write/erase PFLASH, DFLASH.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Arkadiusz,

There is no need to disable both if you modify only one of them.

 

Regards,

Daniel

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Arkadiusz,

Thank you for the report, it has been forwarded to SDK design team and it will be fixed.

The cache should be disabled before modifying the flash content because the buffer is not updated automatically. 

Regards,

Daniel

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dsfire
Contributor III

Hi Daniel,

Which documents mentioned these "The cache should be disabled before modifying the flash content because the buffer is not updated automatically"?

Should i disable instruction cache before modifying corresponding flash content with the following statement?

LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1);

Thanks.

Regards,

Liu

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Liu,

This is not explicitly required but recommended, this is on the user's responsibility. 

You could refer to AN4745 Optimizing Performance on Kinetis K-series MCUs

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BR, Daniel

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dsfire
Contributor III

Hello Daniel,

Thanks for your reply.

Regards,

Liu

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