S32K ECC functionality

[andals]

We are trying to understand which memory types of the S32K is protected by ECC. It is clear from the S32K1xx Series Reference Manual that both sections of RAM is protected as well as how to detect both single-bit and double-bit ECC errors. For the FlexNVM module it is also clear that if it is configured as Data Flash or Emulated EEPROM, single-bit ECC errors are automatically corrected and how to detect double-bit ECC errors. If CSEc is used, it is also clear that CSE_PRAM area is protected.

However, for the regular data/program flash (ex in S32K148 address range: 0000_0000-0017_FFFF ), it is not clear for us from the Reference Manual or other S32K documentation if it is ECC protected and how. It seems like double-bit faults in regular flash is reported in register FTFC->FERSTAT->DFDIF (Double Bit Fault Detect Interrupt Flag). Is this correct? For single-bit faults in regular flash there is less information:  Is it in place for regular flash? Is it automatically corrected? Is there any reporting of it?

Best regards,

André

[durga_choudhury]

I have a few related questions on this topic:

1. Is there a way, either in software or hardware, to 'scrub' memory that needs ECC correction? ('scrubbing' means writing back the correct value to the memory location so it won't need ECC correction next time).

2. In case of double bit errors, how is this reported? Does the user application need to read the register mentioned in this discussion or is there some asynchronous (e.g. interrupt) method also exists?

Thanks for your help

Durga Choudhury

[lukaszadrapa]

Hi,

program and data flash is protected by ECC too.

Are you aware of this application note?

https://www.nxp.com/docs/en/application-note/AN12522.pdf

It should answer all your questions.

Regards,

Lukas

[andals]

@lukaszadrapa 

After reading the application note, it is still a bit unclear to us about the single-bit fault for flash. Following information exist in the application note:

The ECC logic implemented in the S32K1xx Flash memory can correct single-bit fault automatically and can detect multiple-bit fault in each NVM sections. The multiple-bit fault is enabled using the FERCNFG[DFDIE] bit. When the multiple-bit error is detected, the FERSTAT[DFDIF] flag is set, and the interrupt request is generated.

• Since the formulation above is "can correct single-bit fault automatically", is there any action needed to turn on the correction?
• Is there any reporting of single-bit faults in flash?

Best regards,

André

[lukaszadrapa]

Hi André,

yes, single bit errors are automatically corrected. This feature can't be turned off.

Reporting can be enabled in Error Reporting Module in CR0 register if needed.

Regards,

Lukas

[andals]

Hi Lukas,

Then our doubts regarding enabling of single bit error correction are clear, thank you!

Regarding Error Reporting, the latest Reference Manual for S32K (Rev. 12.1, 02/2020) states that the mentioned register is used only for RAM error reporting. Is this not the case?

 

Best regards,

André

[lukaszadrapa · Accepted solution]

That's a good point, you are right. Sorry, I mismatched that with another devices where it is possible.

I just confirmed that there's no flag for single bit error. Only double bit error can be reported on flash.

Regards,

Lukas

[andals]

Thank you Lukas for your fast support in this matter! 

Have a nice evening.

Best regards,

André

[andals]

@lukaszadrapa 

Thank you for the quick reply! We have not seen this specific application note, we will review it and hopefully it should clear out our doubts.

Best regards,

André