Question about S32K3 SPI communication speed and data width

[Berke_E]

Hello everyone,

I'm working on the S32K312-Q172 device with SPI communication , and I need to implement the wakeup_sleep command, which requires keeping the chip-select (CS) line low for about 350 microseconds. In my Simulink model, I’m using an SPI_SetupEB block (see the first figure) to send a single “dummy byte” of 0xFF.

1. CS Low Duration
   How can I verify or measure that this block is actually driving the CS line low for the required 350 microseconds? Is there a recommended way to confirm the exact time the CS pin remains low when using the SPI_SetupEB block?

2. DataWidth vs. SpiEbMaxLength
   Additionally, I would like to send 4 bytes of data in another scenario. In the block parameters, there is a SpiDataWidth field and a SpiEbMaxLength field. I’m confused about the difference between them. For instance, if I want to transmit 4 bytes (which is 32 bits), do I set SpiDataWidth to 8 and SpiEbMaxLength to 32? Or do I set SpiDataWidth to 32 directly? How exactly do these two parameters interact to handle multi-byte transmissions?

Any guidance would be appreciated.

Thank you!

[Berke_E]

Hi @VaneB,

I added the delays as you suggested, but as shown in the first figure, even though I set both the Clk2Cs and Cs2Clk values to 180 microseconds (within the allowed range), the errors shown in the second figure occur. I can’t figure out the problem. Is that issue about my Evaluation board S32K312-Q172? Is there another way to keep the CS pin low for 350 microseconds? In the third figure, I turned the Spi_setupEB block into a subsystem and used a 350 microsecond delay in the Stateflow chart. Would it work that way?

Thank you.

[VaneB]

Hi @Berke_E 

Instead of using the CS pin from the SPI, I would suggest considering the use of a GPIO as your CS. This way, you can have more control over the state of the select pin, manipulating it according to your specific requirements, as you can directly manage its state (high or low) from your code, adapting it to the needs of your application.

[Berke_E]

Hello @VaneB ,

As you suggested, I am trying to assign and use the CS signal on a GPIO pin. I've set up the configuration as shown in the image, but now I'm a bit confused about how to proceed further. I have a couple of questions regarding this setup:

1. According to the pin map for the S32K312-Q172 board, PTB25 (J3.6) is assigned as the default CS for the master instance. Can I use this pin for manual control, or should I choose a different one?

2. Once I assign the pin, how can I control the CS signal (i.e., drive it low and high) in Simulink? Could you please provide more details on which blocks to use and how to configure them for this purpose?

Thank you for your assistance.

[VaneB]

Hi @Berke_E 

In the User Manual for the S32K3_S32M27x SPI Driver, there is a dedicated section that explains how to configure handling Chip Select via general-purpose IO.

I recommend reviewing this document along with the S32K3_S32M27x SPI Driver Integration Manual included with the RTDs. These documents provide detailed information about the driver, including its limitations, hardware and software requirements, usage instructions, and configuration guidelines. They will be helpful for gaining a deeper understanding of the driver's functionality. You can find these resources at the following location:

C:\NXP\SW32K3_S32M27x_RTD_R21-11_5.0.0\eclipse\plugins\Spi_TS_T40D34M50I0R0\doc.

Regarding implementation in Simulink, I am not familiar with it, but Model-Based Design Tools (MBDT) are supported by our engineers through the NXP Community - Model-Based Design Toolbox (MBDT).

[VaneB · Accepted solution]

Hi @Berke_E 

To implement your solution, use configurable delays between transfers, SCK to PCS, and PCS to SCK. When multiple data items are sent in the same package, the delay between each data transfer will be the sum of the delays configured for these three parameters.

For better reference, in the image above, I have marked the PCS-to-SCK Delay (CCR[PCSSCK]) in blue, the SCK-to-PCS Delay (CCR[SCKPCS]) in orange, and the Delay Between Transfers/PCS-to-PCS (CCR1[PCSPCS]) in red.

Regarding the difference between SpiDataWidth and SpiEbMaxLength, please refer to the following community post where this topic has already been discussed.

What's the difference between SpiDataWidth and SpiEEMaxLenght

BR, VaneB