Question Regarding LIN Baud Rate Deviation on S32K312

[dongxun]

Dear NXP Support Team,    

  I am a developer working with the S32K312 MCU and have a question regarding LIN communication configuration.     When configuring the LIN driver using EB Tresos 28.2 and RTD 4.4.2 for the S32K312, I set the baud rate to 19200 bps. However, during communication testing, CANoe displays the master's actual baud rate as approximately 19530 bps. dongxun_0-1765787307854.png

This represents a deviation of about 1.7% from the configured value, which exceeds the LIN 2.1 specification requirement of less than 0.5% deviation between actual and nominal baud rates.

dongxun_1-1765787331807.png

I understand that the actual LPUART baud rate is calculated based on SBR and OSR values. dongxun_2-1765787353268.png

dongxun_3-1765787366925.png

With my current clock configuration of 30MHz, some calculation deviation is expected. My specific questions are:

1. Are there recommended methods to minimize this deviation and better align the actual baud rate with the configured value?
2. Is adjusting the clock frequency the only available solution, or are there other configuration approaches I could consider?

I would greatly appreciate your expert advice on this matter. Thank you for your time and support. Best regards, dongxun

[danielmartynek]

HI @dongxun,

You should achieve 19181.6 bps with the following configuration:

OSR: 16
SBR: 92

30MHz / (92 + 17) = 19181.6 bps

Which RTD version are you using? You mentioned the AUTOSAR version, but not the RTD version.
It appears that the generated values for OSR and SBR are incorrect.
Could you confirm whether the LPUART clock reference in the MCU driver is really set to 30 MHz?

Regards,

Daniel

[dongxun]

Hi Daniel,  

    I am using RTD version SW32K3_RTD_4.4_2.0.2_D2211. I am aware that this is a relatively old version, but given the current project progress, switching to a new version is not an easy task.   I have rechecked the clock-related configurations in MCAL. As shown in the attached image, the reason for selecting the above clock configuration is as follows: according to the reference manual, all LPUART instances except LPUART0 should use ALPS_SLOW_CLK. Additionally, my Core_CLOCK is 120 MHz. Following Option B in the chip manual, I configured AIPS_PLAT_CLK and AIPS_SLOW_CLK to 60 MHz and 30 MHz, respectively. Then, LIN references AIPS_SLOW_CLK, which is 30 MHz. I believe this configuration should be correct. However, the current phenomenon indicates that the actual clock frequency is apparently higher than 30 MHz, leading to a higher calculated baud rate.

dongxun_0-1765846296291.png

dongxun_1-1765846316145.png

Attached are my configuration files for your reference.

[danielmartynek]

Hello @dongxun,

The clock signal can be monitored on the CLKOUT pin.
This is the most reliable method to verify that the clock is configured correctly.

Have you tried updating the generated file with the following values?

OSR: 16
SBR: 92

After initializing the LPUART, check the actual register settings and measure the baud rate again.

Regards,

Daniel