NXP s32k312 SRAM MultibitError

[Anitha7]

@danielmartynek 

I’m able to hit the SRAM ISR (ERM0_ISR_Handler) for single-bit errors, but the handler is not being called for multi-bit errors.

As far as I understand, a non-correctable error event corresponds to a multi-bit error, correct?

I can see that the SRAM non-correctable error event bit is set in SR0, but the ISR is not being triggered.

Could you please help me understand how to call the multi-bit error ISR?

I enabled interrupt notification for SRAM0 in CR0 register also

[danielmartynek]

Hi @Anitha7,

I updated the example by adding uncorrectable error injection into SRAM0.

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-SRAM-Baremetal-v3-0-S3...

Can you read the VTOR register in your application?

The interrupt vector table must not reside in SRAM0 when injecting an uncorrectable ECC fault into the memory.

Otherwise, the ECC fault would corrupt the vector table during a fetch leading to another fault exception.

Regards,

Daniel

[Anitha7]

Hi @danielmartynek 

VTOR table points to flash memory only during SRAM0 inject uncorrectable ECC fault.

I configured the system for an SRAM0 as per your reference example code. uncorrectable ECC fault occur by setting the corresponding bit in the SRO register.

I enabled interrupt notification in corresponding CR0 register.

After uncorrectable ECC fault occurs, control transfers to the system call function, software not working after that until i perform reset. The ERM_1_Handler is not being triggered, even though I have added it. For single-bit errors, the ERM_0_Handler is triggered correctly.

What should I do to ensure that the ERM_1_Handler is invoked when a multi-bit (uncorrectable) ECC error occurs?

Also, just to confirm — does a multi-bit error always indicate an uncorrectable ECC fault?

[danielmartynek]

Hi @Anitha7,

What do you mean by a multi-bit error?

There is one 8-bit checksum for 64bits (8 bytes) of data, it is not possible to detect every posilble ECC error. There is ECC SECDED (Single error correction, Double error detection).

Regards,

Daniel

[Anitha7]

hi @danielmartynek 

Multibit means Double bit as per RM

I configured the system for an SRAM0 as per your reference. uncorrectable ECC fault occur(NEC0) by setting the corresponding bit in the SRO register.

I enabled interrupt notification for NEC0 and single bit event in corresponding CR0 register.

After Non correctable ECC fault occurs, control transfers to the system call function, software not working after that until i perform reset. The ERM_1_Handler is not being triggered, even though I have added it. For single-bit errors, the ERM_0_Handler is triggered correctly.

What should I do to ensure that the ERM_1_Handler is invoked when a multi-bit (uncorrectable) ECC error occurs?

Also, just to confirm — does a multi-bit error(double bit error) always indicate an uncorrectable ECC fault?

After Non correctable ECC event occurs i need to perform reset run in ECU in normal mode

[danielmartynek]

Hi @Anitha7,

Uncorrectable faults trigger a CM7 fault exception.
In the example I linked, I enabled the Bus_Fault exception, but with a lower priority than the priority of the ERM handler so that the ERM handler is called first.

I believe this might be the issue in your project.

Also, double-check the VTOR pointer and ensure that the ERM interrupt is enabled in the NVIC. You may notice the interrupt pending in NVIC.