NXP S32k312 ERM Module Understanding

[Anitha7]

Hi @lukaszadrapa 

I’m working on the NXP S32K312 microcontroller and want to detect RAM and ROM memory errors.
I found the Error Reporting Module (ERM) in the Reference Manual and have already enabled its clock.
Is that enough to detect SRAM errors just by reading the ERM status registers?
I don’t want to use any drivers like SPD or FCCU or SAF framework.
Also, the Reference Manual mentions that during initialization we need to write some data into memory — what does that mean?
What is an ECC codeword, and how do we write it?

[petervlna]

Hello,

Do I need to manually activate ECC detection, or is it enabled by default?

ECC is enabled by default for both internal SRAM and Flash (ROM) on the S32K312. You do not need to manually activate ECC. It is always on and cannot be disabled via software.

I would like to check for multi-bit errors in the internal RAM and ROM of the NXP S32K312. Could you please guide me on how to enable ECC (Error Correction Code) for both RAM and ROM?

To detect multi-bit ECC errors:

1. Ensure memory is accessed (read/write).
2. Monitor ERM status registers (e.g., ERM_SR0, ERM_ESR0).
3. Optionally configure FCCU to handle fault escalation.
4. You can also use the EIM (Error Injection Module) to simulate multi-bit errors for testing.

Best regards,

Peter

[Anitha7]

Hi @petervlna 

According to the NXP S32 Reference Manual, I followed the steps to inject a RAM error:

1. Enabled the SRAM0 channel.

2. Configured the EICHD0_WORDm[CHKBIT_MASK] and EICHD0_WORDm[Ba_bDATA_MASK] fields for the channel used to inject the error.

3. Programmed the EICHEN register to enable the corresponding injection channel.

4. Set the EIMCR[GEIEN] bit to globally enable all configured error injection channels.

To create a multi-bit error, I inverted two bits in either the CHKBIT_MASK or DATA_MASK fields of the EICHDn_WORD registers.

After that, I configured the ERM (Error Reporting Module) to monitor error status. However, when I checked the ERM_SR0 register after performing the multi-bit injection, I did not see any error status reported.

Could you please help me understand how to detect the multi-bit error status correctly? I have already enabled the ERM module clock. Is there anything else that needs to be configured?

Also, as per the reference manual, ECC is enabled by default for both RAM and ROM. Is that correct?

Note: I don't want to use any external drivers like SPD or SAF for RAM checking

During startup i am performing SRAM memory initialization

Could u help how can i do RAM and ROM checks without Drivers (SPD and SAF)

[petervlna]

Hello,

Also, as per the reference manual, ECC is enabled by default for both RAM and ROM. Is that correct?

Yes, ECC is enabled by default and cannot be disabled.

Could u help how can i do RAM and ROM checks without Drivers (SPD and SAF)

Best is to follow reference manual.

After that, I configured the ERM (Error Reporting Module) to monitor error status.

that is correct.

I did not see any error status reported.

As there is nothing to configure in ERM for reporting of status of detected ECC error, I assume your error was not injected. Otherwise you will see it in SRx register of ERM.

Did you perform read of the address where you inject the error? The ECC will come when you read the corrupt address. As ECC mechanism will compare the data in the memory with syndrome and then decide if it match. Such can be done only on reads.

Best regards,

Peter

[Anitha7]

Hi @petervlna 

Thank you for your response.

I configured the system for an SRAM0 as per your reference. uncorrectable ECC fault occur(NEC0) by setting the corresponding bit in the SRO register.

I enabled interrupt notification for NEC0 and single bit event in corresponding CR0 register.

After Non correctable ECC fault occurs, control transfers to the system call function, software not working after that until i perform reset. The ERM_1_Handler is not being triggered, even though I have added it. For single-bit errors, the ERM_0_Handler is triggered correctly.

What should I do to ensure that the ERM_1_Handler is invoked when a multi-bit (uncorrectable) ECC error occurs?

Also, just to confirm — does a multi-bit error(double bit error) always indicate an uncorrectable ECC fault?

After Non correctable ECC event occurs i need to perform reset run in ECU in normal mode

[petervlna]

Hello,

Is enabling the ERM clock enough to detect SRAM errors?

Not quite. Enabling the ERM clock is just the first step. The Error Reporting Module (ERM) itself doesn't actively scan memory — it monitors and reports errors that are detected by other subsystems, like the ECC (Error Correction Code) logic in the SRAM controller.

To detect SRAM errors:

• The SRAM must be accessed (read or written).
• ECC logic must be enabled and properly initialized.
• ERM will then log any ECC-detected errors in its status registers.

So, just reading ERM status registers won't detect errors unless ECC is active and memory is accessed.

What does “write some data into memory during initialization” mean?

This refers to initializing ECC codewords. ECC works by storing redundant bits alongside your actual data to detect and correct errors. When memory is first powered up, it contains undefined values, and the ECC bits are not valid.

To avoid false ECC errors, you must:

1. Write known data to each ECC-protected memory location. (RAM)
2. This causes the ECC logic to generate and store a valid ECC codeword for that data.

What is an ECC codeword?

An ECC codeword is a combination of:

• Your actual data bits
• ECC bits (redundant bits used for error detection/correction)

For example, in a single-bit error correction scheme:

• You might have 64 bits of data + 8 bits of ECC = 72-bit codeword.

When you write to memory:

• The ECC logic calculates the ECC bits based on your data.
• It stores both the data and ECC bits.
• On read, it checks the ECC bits to detect/correct errors.

No SPD, FCCU, or SAF?

That’s fine — you can still use ERM + ECC directly. Just make sure:

• ECC is enabled in the SRAM controller.
• You initialize memory properly.
• You periodically check ERM status registers for error flags.

Best regards,

Peter

[Anitha7]

Hi @petervlna 

Thank you for your informative response.

I am not using any external SARM controller.

I would like to check for multi-bit errors in the internal RAM and ROM of the NXP S32K312. Could you please guide me on how to enable ECC (Error Correction Code) for both RAM and ROM?

Do I need to manually activate ECC detection, or is it enabled by default?

Additionally, could you please help me better understand how ECC works in this context?

[petervlna]

Hello,

Could you please guide me on how to enable ECC (Error Correction Code) for both RAM and ROM?

There is nothing to guide here are the ECC detection is always on.

Do I need to manually activate ECC detection, or is it enabled by default?

See above.

Additionally, could you please help me better understand how ECC works in this context?

Sure, just go trough this AN:

https://www.nxp.com/docs/en/application-note/AN12522.pdf

The ECC mechanism is the same.

Best regards,

Peter