NXP S32k118 I2C emulation

[Luke_John]

Hello,

I am evaluating an approach to drive 10 identical-address I2C slaves simultaneously from an S32K118 (Q48) master without using an I2C multiplexer.

My plan is to emulate 10 parallel I2C buses by using a hardware timer to generate the clock, combined with DMA transfers to simultaneously update 10 GPIO pins on the same port.

Could you help confirm if the S32K118’s DMA and timer peripherals support triggering port-wide GPIO updates in this manner? Are there any hardware limitations or edge cases I should be aware of with this architecture?

Best regards,

[danielmartynek]

Hi @Luke_John,

Yes, this architecture does fundamentally support.

Refer to S32K1xx Series Reference Manual, Rev. 14:

Section 13.3.1 GPIO register descriptions.

As you can see, all the GPIO ports are accessible from 32bit registers.

Section 17.4.1 "Using the GPIO ports to drive or sample waveforms By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip memory."

The DMA tranfers can be triggered by a timer through DMAMUX, TRGMUX.

Crossbar must be programmed to round-robin arbitration (configuring MCM_CPCR[CBRR] as '1') for seamless DMA transfers.

Regards,

Daniel