Hi,
unfortunately I do not see any HW related root of cause within FlexCAN. If SW is preparing TX MB for transmission and the MB wins internal arbitration a message would be transmitted at the first opportunity window on the bus. A node can lost bus arbitration and leave a bus, but I do not guess that.
A automatic bus off recovery takes about that 3ms, but only in case bus is idle, if not it can be extended. TXERRCNT is cascaded with another internal counter to count the occurrences of 11
consecutive recessive bits on the bus. TXERRCNT is reset to zero. It counts in a manner where the internal counter counts 11 such bits and then wraps around when incrementing the TXERRCNT. When TXERRCNT reaches the value of 128, ESR1[FLTCONF] is updated to Error Active, and both error counters are reset to zero. Upon any instance of a dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the TXERRCNT value.
BR, Petr