NXP S32K144 SPI Communication Issue with eSE Chip - SPI Comunication is not working

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NXP S32K144 SPI Communication Issue with eSE Chip - SPI Comunication is not working

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ajay_jadav5
Contributor I

Dear NXP Semiconductor Support Team,

I hope this email finds you well. We are currently encountering a critical issue with SPI communication between the NXP S32K144 controller and our eSE (embedded Secure Element) chip. As a trusted supplier of advanced semiconductor solutions, we are seeking your expertise to resolve this pressing challenge.

Our team has been dedicated to integrating the NXP S32K144 controller into our system, specifically utilizing SPI communication to interface with the eSE chip for secure data exchange. Unfortunately, despite our diligent efforts, we are facing a significant obstacle. The SPI transfer function, which is designed to transmit data between the S32K144 controller and the eSE chip, is producing inconsistent and unexpected outcomes.

Upon analyzing the SPI communication using logic analyzers, we have observed that the transmitted values vary unexpectedly with each transfer. It appears that some crucial bits are missing or being mishandled during the transmission process. Despite adhering closely to the technical documentation and recommended guidelines provided by NXP, we have not been able to identify the root cause of this issue.

In light of the severity of this problem, we urgently request your guidance and support in addressing the SPI communication anomaly between the NXP S32K144 controller and our eSE chip. Specifically, we are seeking:

1. Immediate assistance in diagnosing the missing or mishandled bits during SPI communication and determining the underlying cause.

2. Recommendations for pinpointing any potential hardware or software configurations that might be contributing to this SPI communication problem.

3. Clarification on any known errata related to the SPI interface on the NXP S32K144 controller, which could shed light on the observed behavior.

4. Any available updates, patches, or firmware revisions that address SPI communication issues on the NXP S32K144 controller.

Given the urgency of this matter, we would greatly appreciate the opportunity to schedule an emergency technical discussion or support session with one of your skilled engineers. This would enable us to share detailed information about our hardware setup, review our SPI communication protocol, and receive real-time guidance on troubleshooting steps.

Your comprehensive knowledge of the NXP S32K144 controller and related technologies is pivotal to resolving this pressing challenge. We are committed to achieving successful integration and secure data exchange between the NXP S32K144 controller and our eSE chip.

We acknowledge and value your ongoing support and partnership. With your expertise, we are confident that we can surmount this SPI communication issue and achieve a seamless integration.

Thank you for your immediate attention to this critical matter. We anticipate your swift response and guidance.

Best regards

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1,202 次查看
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @ajay_jadav5,

I'm sorry for the delay, our team is currently overloaded.

Q1. Immediate assistance in diagnosing the missing or mishandled bits during SPI communication and determining the underlying cause.
A1. Can you show the signals captured by a logic analyzer?
Is the SCK clock stable while the MOSI bits are missing?

Q2. Recommendations for pinpointing any potential hardware or software configurations that might be contributing to this SPI communication problem.
A2. What is the CFGR1[SAMPLE] configuration?
I would recommend SAMPLE = 0 unless the baudrate is too high (LPSPI specified in the DS).

Is SAMPLE = 0, the LPSPI samples the internal SCK signal. That means that any external noise on the line does not impact the transmission.

danielmartynek_0-1691743637020.png

 


Q3. Clarification on any known errata related to the SPI interface on the NXP S32K144 controller, which could shed light on the observed behavior.
A3. Errata are listed here: https://www.nxp.com/docs/en/errata/S32K144_0N57U.pdf

Q4. Any available updates, patches, or firmware revisions that address SPI communication issues on the NXP S32K144 controller.
A4. It depends on what NXP drivers and IDE you use, SDK or RTD and which version?

 

Thank you,

Best regards,
Daniel

 

 

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