Hi @ekmas-19,
Refer to the S32K3xx Safety Manual available in the S32K3xx secure files.
ERM is the Error Reporting Module that provides interrupt notification as well as status and address registers for reported ECC faults. However, it does not inject faults. For error injection, there is the EIM (Error Injection Module), which can inject ECC errors into all supported memories. The ECC on memories (both volatile and nonvolatile) cannot be disabled. It is reported by the CM7 core (fault exception), reported by the ERM if enabled, and non-correctable faults can be mapped to the FCCU.
NXP provides SAF and SPD drivers that use the FCCU instead of ERM interrupt notification. Optionally, ERM can be enabled for single‑bit errors, which are corrected by the hardware anyway.
There are SAF and SPD demos (EB Tresos configuration) that show how to inject ECC faults. Also, here is a very simple bare‑metal example: https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-SRAM-Baremetal-v3-0-S3...
Regarding the classic Pattern Match approach, the S32K3xx series supports MBIST in HW. There is the Self-Test Control Unit (STCU2), which triggers MBIST. Again, the SPD and SAF software provides drivers for this functionality.
MBIST rewrites memories, so it is destructive and can only be performed at startup, or the MCU must be reset afterward. It also does not detect runtime errors, whereas ECC is always active and reports single and double‑bit errors when memories are accessed. Therefore, MBIST detects latent hardware faults in SRAM cells, while ECC detects SEUs, transient faults, and runtime corruption. ECC error‑injection tests via EIM validate safety mechanism behavior.
Regards,
Daniel
