Maximum SPI frequency in VLPS?

[nathand]

I have my S32K148 configured as a SPI slave, and am using VLPS mode with DMA wake-up after a SPI transfer completes (after which, it stays in run until it receives an explicit command over SPI to go back to VLPS). I'm expecting that I need to reduce the SPI clock frequency (generated by the master) while in VLPS, but in testing I'm finding that transfers succeed at full speed (SPI data clock at 12mhz) in VLPS. Why? Am I doing something wrong? Is this an indication I'm not successfully entering VLPS? Does the DMA wake-up enable the full-speed clock fast enough to allow the transfer to succeed? At what point in the SPI transfer does the DMA wake-up begin?

More details:
In normal run mode I'm clocking the SPI peripheral at 48mhz through FIRC, and the SPI master generates a 12mhz data clock. In VLPS, I set the SPI peripheral clock source to SIRCDIV2, which is SIRC/2 (4mhz) so I expect I can run SPI transfers at 2mhz.

[nathand]

Thanks. I'm not sure what I'd been doing wrong, but I now have more of my system working, and found that I do need to reduce the SPI data clock frequency when the MCU is in VLPS.

[danielmartynek · Accepted solution]

Hello Nathan,

I'm sorry for the delay.

The LPSPI VLPR specification applies to VLPS as well.

We can't guarantee proper functionality of the module at higher bit rates.

S32K1xx Datasheet, rev.13

DMA wake-up operation is explained in details in the RM, rev12.1 Section 39.4.3.

You can verify the MCU is in VLPS by measuring the VDD consumption and BUS_CLK on an CLKOUT pin.

Regards,

Daniel