LPUART eDMA in Zephyr RTOS

[NFRED]

Hi all, I am currently working on a DMX driver, which runs using the LPUART driver. At the moment I am running in an issue with using the eDMA in Zephyr, where the interrupt never fires correctly and thus never sets the tx line back to idle state. 

I am mostly using the eDMA config from the lpuart_edma example. I am using Zephyr OS for scheduling but do to needing as little cpu cycles i want to use the nxp drivers directly.

Can anyone help? see software and screenshots below.

#include <zephyr/kernel.h>

#include <zephyr/irq.h>

#include <zephyr/device.h>

#include "../lpuart/fsl_lpuart_edma.h"

#include "../dmamux/fsl_dmamux.h"

#include "fsl_iomuxc.h"

#include "dmx.h"

#define LPDMX3LPUART3

#define LPUART_DMA_BASEADDR DMA0

#define LPUART_DMAMUX_BASEADDR DMAMUX

#define LPUART_TX_DMA_CHANNEL 0U

#define DMX_FRAME_SIZE512

static uint8_t dmx_tx_buffer[DMX_FRAME_SIZE] __attribute__((section(".nocache")));

lpuart_edma_handle_t g_lpuartEdmaHandle;

edma_handle_t g_lpuartTxEdmaHandle;

volatile bool txOnGoing = false;

void LPUART_UserCallback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData) {

if (status == kStatus_LPUART_TxIdle) {

txOnGoing = false;

    }

}

void lpuart3_tx_dma_irq_handler(const void *arg) {

EDMA_HandleIRQ((edma_handle_t *)arg);

}

void send_break(void){

LPDMX3->CTRL = 1<<13;

LPDMX3->CTRL = 1<<13;

LPDMX3->CTRL = 1<<13;

LPDMX3->CTRL = 1<<13;

}

void dmx_hal_init(void) {

lpuart_config_t config;

edma_config_t edmaConfig;

CLOCK_EnableClock(kCLOCK_Lpuart3);

IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0U);

IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0U);

LPUART_GetDefaultConfig(&config);

config.baudRate_Bps = 250000; // Standard DMX

config.stopBitCount = kLPUART_TwoStopBit;

LPUART_Init(LPDMX3, &config, CLOCK_GetFreq(kCLOCK_Lpuart3));

DMAMUX_Init(LPUART_DMAMUX_BASEADDR);

DMAMUX_SetSource(LPUART_DMAMUX_BASEADDR, LPUART_TX_DMA_CHANNEL, kDmaRequestMuxLPUART3Tx);

DMAMUX_EnableChannel(LPUART_DMAMUX_BASEADDR, LPUART_TX_DMA_CHANNEL);

EDMA_GetDefaultConfig(&edmaConfig);

EDMA_Init(LPUART_DMA_BASEADDR, &edmaConfig);

EDMA_CreateHandle(&g_lpuartTxEdmaHandle, LPUART_DMA_BASEADDR, LPUART_TX_DMA_CHANNEL);

LPUART_TransferCreateHandleEDMA(LPDMX3, &g_lpuartEdmaHandle, LPUART_UserCallback, NULL, &g_lpuartTxEdmaHandle, NULL);

IRQ_CONNECT(DMA0_DMA16_IRQn, 5, lpuart3_tx_dma_irq_handler, &g_lpuartTxEdmaHandle, 0);

irq_enable(DMA0_DMA16_IRQn);

}

void dmx_send_frame(const uint8_t *src_data) {

// if (txOnGoing) return;

memcpy(dmx_tx_buffer, src_data, DMX_FRAME_SIZE);

lpuart_transfer_t xfer = {

        .data = dmx_tx_buffer,

        .dataSize = DMX_FRAME_SIZE

    };

txOnGoing = true;

if (kStatus_Success != LPUART_SendEDMA(LPDMX3, &g_lpuartEdmaHandle, &xfer)) {

txOnGoing = false;

printk("DMA Transfer Failed!\n");

    }

}

Code ends up in 

(void)arch_irq_lock();

for (;;) {

        /* Spin endlessly * }

Thanks in advance

[danielmartynek]

Hi @NFRED,

You did not specify the MCU part number.

In general, you should double‑check the LPUART eDMA interrupt configuration in both the modules and the NVIC.
It could be that instead of the ISR implemented in the project, an unimplemented ISR is firing, which would call the default ISR and result in a fatal error.

Regards,

Daniel

[NFRED]

Hi @danielmartynek 

Thanks for the reply! I am working on a MIMXRT1064.

I already thought something like a unimplemented ISR, since in the serial logger it says unhandles interrupt:0, but if I enabled that channel, it would just return a different channel.

[Gavin_Jia]

Hi @NFRED ,

Thanks for your interest in NXP MIMXRT series!

If you are using Zephyr, we recommend that your application also use the UART_Async_API. Mixing MCUXSDK and Zephyr implementations may cause issues; for example, certain DMA might be enabled by default in the Zephyr framework or reserved for other peripherals. Additionally, I’ve reviewed your code and noticed a few points that may require attention:

1. lpuartConfig.enableTx/Rx must be manually set to true;

2. For non-cached regions, it is best to use the Zephyr style:

CONFIG_NOCACHE_MEMORY=y

#define DMA_NOCACHE __nocache

static DMA_NOCACHE uint8_t rx_buf1[RX_BUF_SIZE];

3. Add handling for DMA_ERROR_IRQn to assist with troubleshooting.

And I found there is a post may help. https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPUART-eDMA-Efficient-asynch-reception-of-bursty...

Best regards,
Gavin