LPSPI TCF and FCF

[sambath_kumar_k]

I am confused between 

• TCF Transfer Complete Flag ISR
• FCF Frame Complete Flag ISR

What I want ? 

I need to send 10spi frames from Master to one of the slave chip one after another, whereas I dont want to have isr for every end frame whereas I want to have isr end of 10 spi frames. I was using mpc5777C where I have EOQ(End Of Queue) isr to have this function,

1. DO I have any option to do the same in S32k ?
2. what is the difference between TCF vs FCF

Note:  I am using DMA to copy tx fifo and DMA to copy from rx fifo. 

[danielmartynek]

Hello sambath_kumar_kardhik@cat.com,

The difference is explained in the RM.
The FCF flag is set every time a frame is complete, and the PCS has negated.
The TCF flag is set when PCS has negated, and the transmit/command FIFO is empty.

So, I think you can use the TCF flag if the DMA can keep the TX FIFO not empty during the transfer, then, the TCF flag will be set once all the 10 frames have been sent (PCS deasserted) and the TX FIFO is empty.
But at the time the TCF flag is set, the DMA RX transfer might be still in progress.
You could use the DMA major loop complete interrupt if the DMA transfers 10 frames from the LPSPI RX FIFO per a major loop.

Regards,

Daniel

[sambath_kumar_k]

What I want?

I want to send 10frames(frame size is 32bits). After 10 frames SPI should not send any message in the SPI bus. I use DMA.

What should be my configuration.

What I observe?

When I set CONTC bit during first 9 frames and in 10th frame, I clear the CONTC bit. Then The transfer is getting halted. What is the theory behind this,

I read the below in the reference manual, the behaviour is contradicting. It says,

Can you please provide a small example code or configuration of the above case.

Thank you,

Kardhik Sambathkumar

Platform Software

Innov & Tech Devel Div

Caterpillar: Confidential Green

[danielmartynek]

Hello sambath_kumar_kardhik@cat.com,

The continuous transfer feature was discussed here:
https://community.nxp.com/message/1319825 

You can keep the CONTC bit = 0 all the time, unless you want to change the command during an ongoing continues transfer without terminating it.

I don’t understand this decription:
“When I set CONTC bit during first 9 frames and in 10th frame, I clear the CONTC bit. Then The transfer is getting halted. What is the theory behind this”.

You just need to write one command and load the transmit data register with the data you want to send.
In case of a continuous transfer (CS asserted between frames), use the CONT = 1 bit in the commands.
The continuous transfer ends when a new command is written to the transmit command register.

BR, Daniel

[sambath_kumar_k]

Hello Daniel,

Thanks for replying to my email,

I want to achieve the following design,

1. I want to transfer 10frames(each frame of framesize is 32bits) one after other without any interrupts to save time. I configured this in DMA so DMA will copy when SPI TDR request for it. I don't have problem here. Ican able to start.

2. My problem is, SPI is keep on triggering DMA, I am not finding ways to stop or halt the SPI after 10frames. I could do it only in ISR after disabling DMA. But the time it activates the isr is OS dependent. I fear that SPI would have triggered DMA some number of times, which will fail my timing requirement. I want to stop transfer after 10 frames ie: SPI should not put any frames in the bus after 10th frame is sent.

3. I want only 10frames to be sent on SPI bus and not more. SO every 10ms I will send 10 frames to configure and read the data from slave chip.

How can I achieve this.

Thank you,

Kardhik Sambathkumar

Platform Software

Innov & Tech Devel Div

Caterpillar: Confidential Green

[danielmartynek]

Hi Kardhik,

You can transfer 10 x 32b per a major DMA loop and trigger one major loop at a time.

Something like this:

SPI DMA problem 

Regards,

Daniel