LPSPI Debugging S32K344

[JoDo]

Hello,

I wrote a small master salve code and tried to verify the function by debugging it.

When I step through the code, it seems that the flags and data registers are reset by themselves (see image below). But when I run the complete code (without stepping) everything is fine. The master is transmitting and the slave is receiving correctly.

I am using the onboard debuger P&E USB MULTILINK and I have also enabled debug in the CR.

Does anyone have an idea what the problem is?

Thanks!

[danielmartynek · Accepted solution]

Hello Johannes,

The RDF flag indicates the state of the RX FIFO.

And the data can be read by any master from the FIFO, not only the CPU and DMA but the debugger too.

You would need to close the register view and the memory view so that the Receive Data Register (RDR) is not read by the debugger.

Regards,

Daniel

[JoDo]

Hello Daniel,

Thank you very much for the quick reply. That was really very helpful.

I guess there is no other way to watch the registers without interfere with them?

Regards,

Johannes

[danielmartynek]

Hello Johannes,

Unfortunately, if the debugger reads the RDR register it is as if the CPU read it.

Regards,

Daniel