LPSPI DMA

[hajianik]

Hi,

My target is S32K148,

I'm doing DMA on LPSPI,

There's something that I can't justify :

DONE bit in the TDR DMA channels for RX/TX don't get set simultaneously whereas I think they should .

When the transfer is complete that means all the data on MOSI,and MISO has been transferred .

I'm under the impression when the major loop has completed its count the transfer is complete.

But my observation is that they are out of phase , when one is set the other is cleared and visa versa.

I assigned same priority of 0 to both channel.

Is this a normal behavior ? or there's something going on.

Please educate me.

Thanks,

Koorosh Hajiani

[danielmartynek]

Hi Koorosh,

If we take a look at the LPSPI module alone, the DMA transfers cannot be triggered/completed at the same time.

The TX DMA channel writes data to the LPSPI TX FIFO and starts an LPSPI transfer.

Once RX data are available in the LPSPI RX FIFO, the RX DMA transfers can start.

BR, Daniel 

[hajianik]

Hi Daniel,

Thanks for your response,

What I can not phantom is if you look at any SPI frame on the scope once the CS is deasserted for example goes back high ,

both set of data transmitted and received are completed.

In other word one the transmit is complete the receive is also complete.

May be I misunderstand your comment. Are you saying three is an actual delay between transmit data completion and receive data completion?

That's hard for me to grasp.

Best Regards,

Koorosh Hajiani

[danielmartynek]

Hi Koorosh,

Yes, there is a delay.

The DMA TX transfer starts before the CS is asserted.

The DMA RX transfer starts only once there are some data in the RX FIFO, when the RDF flag is set.

Regards,

Daniel

[hajianik]

Hi Daniel

You're correct, I was confusing SPI TRANSFER COMPLET with DMA transfer DONE.

Thanks

[hajianik]

Hi Daniel,

So in that case,  DMA RECEIVE DONE interrupt  when triggered is an indication that the entire transfer is complete.

Is that correct?

Thanks,

Koorosh Hajiani

[danielmartynek]

Hi hajianik@gmail.com,

I don't know how exactly you implemented it.

But in general, the DMA transfer from the LPSPI RX FIFO can start when LPSPI_SR[RDF] == 1 which means that, at that time, at least a part of the SPI transfer has been already completed. 

Regards,

Daniel

[hajianik]

Hi Daniel,

There is this DMA major loop done interrupt which triggers when the DMA MAJOR LOOP COUNT is equal to what is in the corresponding

DMA descriptor, so lets say your packet consists of 5 bytes , then you set the major loop count to 5, once 5 loop completes it'll trigger an interrupt.

At least this is my understanding.

What do you think?

Thanks,

Koorosh

[danielmartynek]

Hi Koorosh, 

Then yes, it should be triggered once both the SPI and the DMA transfer is complete.

Do you see any problem with that?

BR, Daniel

[hajianik]

Hi Daniel,

I've not implemented this yet.

I will try to code it today or first thing on Monday and I'll let you know how it goes.

This an attempt to use CPU load and avoid to wait for the transfer to complete before starting the next transfer .

if this works you can trigger the 1st asynchronous transfer and CPU is free to do other task until the interrupt triggers and right then and there you start the next transfer.

Thanks, 

Koorosh Hajiani